Module x86 

Modules

cpuid

Structs

AmdC001102dMsr

Layout for [AMD_C001102d].

AmdC0011028Msr

Layout for AMD_C0011028.

AmdC0011029Msr

Layout for AMD_C0011029.

AmdHardwareConfigurationMsr

Layout for MSRC001_0015.

AmdLoadStoreConfigurationMsr

Layout for AMD_LOAD_STORE_CONFIGURATION.

ApicIdDecoder

ApicIdDecoder is a utility for extracting particular topological level IDs from an (x2)APIC ID.

ArchCapabilitiesMsr

Layout for IA32_ARCH_CAPABILITIES.

ControlRegister0

The layout of CR0.

ControlRegister2

The layout of CR2.

ControlRegister3

The layout of CR3.

ControlRegister4

The layout of CR4.

ControlRegister8

The layout of CR8.

ControlRegister3Pcid

The layout of CR3_PCID.

CpuCacheInfo

Gives information on the set of caches in a package.

CpuCacheLevelInfo

Represents a single cache.

ExtendedControlRegister0

[intel/vol3]: 2.6 Extended Control Registers

MiscFeaturesMsr

Layout for IA32_MISC_ENABLE.

SpeculationControlMsr

Layout for SPECULATION_CONTROL.

TsxControlMsr

Layout for IA32_TSX_CTRL.

VirtualSpeculationControlMsr

Layout for VIRTUAL_SPECULATION_CONTROL.

X86ExtendedFeatureEnableRegisterMsr

Layout for IA32_EFER.

Enums

SpectreV2Mitigation

An architecturally prescribed mitigation for Spectre v2.

Vendor

Enumeration of vendors.

Constants

AMD_C001102D

[amd/rg/17h/00h-0Fh] references bit 34.

AMD_C0011028

[amd/rg/17h/00h-0Fh] references bit 4.

AMD_C0011029

[amd/rg/17h/00h-0Fh] references bit 13.

AMD_LOAD_STORE_CONFIGURATION

[amd/ssbd] references bits 10, 33, 54. [amd/rg/17h/00h-0Fh] references bits 4, 57.

CR0

[intel/vol3]: 2.5 Control Registers: CR0

CR2

[intel/vol3]: 2.5 Control Registers: CR2

CR3

[intel/vol3]: 2.5 Control Registers: CR3 without PCID feature

CR4

[intel/vol3]: 2.5 Control Registers: CR4

CR8

[intel/vol3]: 2.5 Control Registers: CR8

CR3_PCID

[intel/vol3]: 2.5 Control Registers: CR3 with CR4.PCIDE enabled

IA32_ARCH_CAPABILITIES

[intel/vol4]: Table 2-2. IA-32 Architectural MSRs (Contd.).

IA32_EFER

[intel/vol3]: 2.2.1 Extended Feature Enable Register [amd/vol2]: 3.1.7 Extended Feature Enable Register (EFER)

IA32_MISC_ENABLE

[intel/vol4]: Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture.

IA32_TSX_CTRL

[intel/vol4]: Table 2-2. IA-32 Architectural MSRs (Contd.).

MSRC001_0015

[amd/ppr/17h/01h,08h]: 2.1.14.2 MSRs - MSRC000_0xxx.

SPECULATION_CONTROL

Speculation control.

VIRTUAL_SPECULATION_CONTROL

Virtual speculation control (e.g., for hypervisor usage).

Functions

apply_x86_errata_workarounds

Applies workarounds to processor-specific errata.

can_mitigate_x86_mds_taa_bugs

Whether the MDS/TAA bugs can be mitigated, which all make use of the same method (MD_CLEAR): https://software.intel.com/security-software-guidance/deep-dives/deep-dive-intel-analysis-microarchitectural-data-sampling#mitigation4processors

can_mitigate_x86_ssb_bug

cycles

Return the current CPU cycle count.

device_memory_barrier

Synchronize all memory accesses of all kinds.

disable_tsx

Attempts to disable TSX and returns whether it was successful.

get_apic_id

Returns the APIC ID - x2APIC if supported - associated with the logical processor in turn associated with the provided Cpuid.

get_preferred_spectre_v2_mitigation

Returns the preferred Spectre v2 mitigation strategy.

has_ibrs

Whether Indirect Branch Restricted Speculation (IBRS) is supported. The “always on” mode refers to an optimization in which IBRS need only be enabled once; IBRS in this mode are also referred to as “enhanced”.

has_stibp

Whether Single Thread Indirect Branch Predictors (STIBP) are supported. The “always on” mode refers to an optimization in which STIBP need only be enabled once.

has_x86_mds_bugs

Whether the CPU is susceptible to any of the Microarchitectural Data Sampling (MDS) bugs.

has_x86_mds_taa_bugs

Whether the CPU is susceptible to any of the MDS or TAA bugs, which are closely related and similarly mitigated.

has_x86_meltdown_bug

Whether the CPU is susceptible to the Rogue Data Cache Load (Meltdown) bug: https://software.intel.com/security-software-guidance/advisory-guidance/rogue-data-cache-load.

has_x86_ssb_bug

Whether the CPU is susceptible to the Speculative Store Bypass (SSB) bug: https://software.intel.com/security-software-guidance/advisory-guidance/speculative-store-bypass

has_x86_swapgs_bug

Whether the CPU is susceptible to swapgs speculation attacks: https://software.intel.com/security-software-guidance/advisory-guidance/speculative-behavior-swapgs-and-segment-registers

has_x86_taa_bug

Whether the CPU is susceptible to the TSX Asynchronous Abort (TAA) bug.

mitigate_x86_ssb_bug

Attempt to mitigate the SSB bug. Return true if the bug was successfully mitigated.

serialize_instructions

Force the processor to complete all modifications to register state and memory by previous instructions (including draining any buffered writes) before the next instruction is fetched.

store_memory_barrier

Ensure all stores that appear before this barrier (in program order) complete before any stores that appear after this barrier.

thread_memory_barrier

Synchronize the ordering of all memory accesses wrt other CPUs.

tsx_is_supported

yield

Yield the processor momentarily. This should be used in busy waits.

yield_processor

Convenience alias for [r#yield].