arch

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Enumerations

enum class X86Interrupt : uint8_t
Name Value Comments
kDivideError 0 --
kDebug 1 --
kNmi 2 --
kBreakpoint 3 --
kOverflow 4 --
kBoundRangeExceeded 5 --
kInvalidOpcode 6 --
kDeviceNotAvailable 7 --
kDoubleFault 8 --
kCoprocessorSegmentOverrun 9 --
kInvalidTss 10 --
kSegmentNotPresent 11 --
kStackFaultException 12 --
kGeneralProtection 13 --
kPageFault 14 --
kX87FloatingPoint 16 --
kAlignmentCheck 17 --
kMachineCheck 18 --
kSimdFloatingPoint 19 --
kVirtualizatoin 20 --
kControlProtection 21 --
kFirstUserDefined 32

32..255 are only generated by `INT $n` instructions or APIC programming,
not by the CPU directly.
kLastUserDefined 255

32..255 are only generated by `INT $n` instructions or APIC programming,
not by the CPU directly.

[intel/vol3]: 6.15 Exception and Interrupt Reference

Defined at line 15 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/interrupt.h

enum class ArmL1ICachePolicy : uint8_t
Name Value
VPIPT 0b00
AIVIVT 0b01
VIPT 0b10
PIPT 0b11

Defined at line 18 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/cache.h

enum class RiscvFeature
Name Value Comments
kSstc 0

Extension for supervisor based timer
kSvpbmt 1

SuperVisor extension for Page-Based Memory Types
kVector 2

The standard V extension for vector support
kZicbom 3

Cache-Block Management Operations
kZicboz 4

Cache-Block Zero Operations
kZicntr 5

Counter CSRs are accessible
kMax 6

Not a real feature, but a bookend that allows us to calculate the largest
underlying enum value.

An enumeration of RISC-V features.

This is not intended to be exhaustive, but rather to include the features

that the kernel currently depends on.

Values should not be prescribed manually and are intended to automatically

increment from 0.

Defined at line 22 of file ../../zircon/kernel/lib/arch/include/lib/arch/riscv64/feature.h

enum class ArmShareabilityAttribute
Name Value Comments
kNone 0b00 --
kOuter 0b10

0b01 is reserved.
kInner 0b11

0b01 is reserved.

The cache shareability attribute for memory regions, as defined by the

TCR_ELx.SHn fields.

[arm/v8]: D13.2.120 TCR_EL1, Translation Control Register (EL1)

[arm/v8]: D13.2.121 TCR_EL2, Translation Control Register (EL2)

Defined at line 27 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/memory.h

enum class X86PagingLevelCount
Name Value
k4 4
k5 5

Defined at line 28 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

enum class ArmSmcccConduit : uint32_t
Name Value Comments
kSmc 0xd4000003

smc #0
kHvc 0xd4000002

hvc #0

[arm/smccc] 2.5.3: Conduits

An SMCCC call is invoked using one of two "conduit" instructions:

Defined at line 31 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

enum class ArmPagingConfiguration
Name Value Comments
k4k30Bit 0

4KiB pages, 2 levels of paging: 30-bit virtual addresses.
k4k39Bit 1

4KiB pages, 3 levels of paging: 39-bit virtual addresses.
k4k48Bit 2

4KiB pages, 4 levels of paging: 48-bit virtual addresses.
k16k25Bit 3

16KiB pages, 1 level of paging: 25-bit virtual addresses.
k16k36Bit 4

16KiB pages, 2 levels of paging: 36-bit virtual addresses.
k16k47Bit 5

16KiB pages, 3 levels of paging: 47-bit virtual addresses.
k64k28Bit 6

64KiB pages, 1 level of paging: 28-bit virtual addresses.
k64k42Bit 7

64KiB pages, 2 levels of paging: 42-bit virtual addresses.

Defined at line 33 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class ArmCacheabilityAttribute
Name Value
kNonCacheable 0b00
kWriteBackReadWriteAllocate 0b01
kWriteThroughReadAllocate 0b10
kWriteBackReadAllocate 0b11

The cacheability attribute of a normal memory regions, as defined by the

TCR_ELx.IRGNn and TCR_ELx.ORGNn fields.

[arm/v8]: D13.2.120 TCR_EL1, Translation Control Register (EL1)

[arm/v8]: D13.2.121 TCR_EL2, Translation Control Register (EL2)

Defined at line 39 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/memory.h

enum class X86PagingLevel
Name Value Comments
kPml5Table 0

Page Map Level 5 Table
kPml4Table 1

Page Map Level 4 Table
kPageDirectoryPointerTable 2 --
kPageDirectory 3 --
kPageTable 4 --

[intel/vol3]: Table 4-2. Paging Structures in the Different Paging Modes

[amd/vol2]: Figure 5-1. Virtual to Physical Address Translation — Long Mode

Defined at line 49 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

enum class ArmDeviceMemory
Name Value Comments
kNonGatheringNonReorderingNoEarlyAck 0b00

nGnRnE
kNonGatheringNonReorderingEarlyAck 0b01

nGnRE
kNonGatheringReorderingEarlyAck 0b10

nGRE
kGatheringReorderingEarlyAck 0b11

GRE

Types of ARM device memory.

Numeric values are as expected by MAIR_ELx attribute encodings for device

memory.

Defined at line 50 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/memory.h

enum class ArmSmcccFunction : uint32_t
Name Value Comments
kSmcccVersion 0x8000'0000

[arm/smccc] 7: Arm Architecture Calls
kSmcccArchFeatures 0x8000'0001

[arm/smccc] 7: Arm Architecture Calls
kSmcccArchSocId 0x8000'0002

[arm/smccc] 7: Arm Architecture Calls
kSmcccArchWorkaround1 0x8000'8000

[arm/smccc] 7: Arm Architecture Calls
kSmcccArchWorkaround2 0x8000'7fff

[arm/smccc] 7: Arm Architecture Calls
kSmcccArchWorkaround3 0x8000'3fff

[arm/smccc] 7: Arm Architecture Calls
kPsciPsciVersion 0x8400'0000

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciCpuSuspend 0xc400'0001

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciCpuOff 0x8400'0002

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciCpuOn 0xc400'0003

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciAffinityInfo 0xc400'0004

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciMigrate 0xc400'0005

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciMigrateInfoType 0x8400'0006

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciMigrateInfoUpCpu 0xc400'0007

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciSystemOff 0x8400'0008

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciSystemReset 0x8400'0009

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciSystemReset2 0xc400'0012

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciMemProtect 0x8400'0013

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciMemProtectCheckRange 0xc400'0014

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciPsciFeatures 0x8400'000a

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciCpuFreeze 0x8400'000b

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciCpuDefaultSuspend 0x8400'000c

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciNodeHwState 0x8400'000d

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciSystemSuspend 0xc400'000e

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciPsciSetSuspendMode 0x8400'000f

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciPsciStatResidency 0xc400'0010

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.
kPsciPsciStatCount 0xc400'0011

[arm/psci] 5.1: Function prototypes
0x8400'0000 - 0x8400'001f and their SMC64 counterparts at
0xc400'0000 - 0xc400'001f are reserved by [arm/smccc] for PSCI.

These are the SMC64 versions when both SMC32 and SMC64 versions are
defined.

[arm/smccc] 6: Function Identifier Ranges

0x8000'0000 - 0x8000'ffff: Arm Architecture Calls

0x8100'0000 - 0x8100'ffff: CPU Service Calls

0x8200'0000 - 0x8200'ffff: SIP Service Calls

0x8300'0000 - 0x8300'ffff: OEM Service Calls

0x8400'0000 - 0x8400'ffff: Standard Secure Service Calls

Defined at line 55 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

enum class X86Msr : uint32_t
Name Value Comments
IA32_EFER 0xc000'0080

Extended Feature Enable Register
IA32_FS_BASE 0xc000'0100

Current %fs.base value.
IA32_GS_BASE 0xc000'0101

Current %gs.base value.
IA32_KERNEL_GS_BASE 0xc000'0102

%gs.base value after `swapgs`.
IA32_SPEC_CTRL 0x0000'0048

Speculation control.
IA32_PRED_CMD 0x0000'0049

Prediction commands.
IA32_ARCH_CAPABILITIES 0x0000'010a

Enumeration of architectural features.
IA32_TSX_CTRL 0x0000'0122

TSX control.
IA32_MISC_ENABLE 0x0000'01a0

Miscellaneous processor features.
IA32_DEBUGCTL 0x0000'01d9

Debug control.
IA32_PERF_CAPABILITIES 0x0000'0345

Performance monitoring features available.
MSR_LBR_SELECT 0x0000'01c8

Control register for the LBR feature
MSR_LASTBRANCH_TOS 0x0000'01c9

Current top of stack of LBRs.
MSR_LASTBRANCH_0_FROM_IP 0x0000'0680

Source information of 0th LBR.
MSR_LASTBRANCH_0_TO_IP 0x0000'06c0

Destination information of 0th LBR.
MSR_LBR_INFO_0 0x0000'0dc0

Additional information of 0th LBR.
MSRC001_0015 0xc001'0015

AMD Hardware Configuration.
MSR_VIRT_SPEC_CTRL 0xc001'011f

Virtualized speculation control.
MSRC001_1020 0xc001'1020

AMD load-store configuration.
MSRC001_1028 0xc001'1028 --
MSRC001_1029 0xc001'1029 --
MSRC001_102D 0xc001'102d --

MSR identifiers. These use the ALL_CAPS name style to be consistent with

the Intel manuals. The generated header

<lib

/arch/x86/msr-asm.h> contains

macros for `MSR_

<name

>` so these constants can be used in assembly code.

Defined at line 61 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/msr.h

enum class VirtualAddressExtension
Name Value Comments
kCanonical 0

Sign-extended (commonly referred to as "canonical"): each unaddressable
bit must match the highest addressable bit.

Conventionally used in paging schemes that configure the upper and lower
spaces together: the subspace that is sign-extended as 0 represents the
lower, while the subspace that is sign-extended as 1 represents the upper.
k0 1

All unaddressable bits are 0.

Conventionally used for describing the lower address space in paging
schemes that configure the upper and lower spaces separately.
k1 2

All unaddressable bits are 1.

Conventionally used for describing the upper address space in paging
schemes that configure the upper and lower spaces separately.

Parameterizes the unaddressable bits of a virtual address.

Defined at line 67 of file ../../zircon/kernel/lib/arch/include/lib/arch/paging.h

enum class RiscvPagingLevel
Name Value
k4 4
k3 3
k2 2
k1 1
k0 0

Defined at line 75 of file ../../zircon/kernel/lib/arch/include/lib/arch/riscv64/paging-traits.h

enum class ArmMaximumVirtualAddressWidth
Name Value
k48Bits 48
k52Bits 52

[arm/v8]: D5.1.3 VMSA address types and address spaces

One of two possible maximum virtual address widths.

Defined at line 87 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class RiscvMemoryType
Name Value Comments
kPma 0

None
kNc 1

Non-cacheable, idempotent, weakly-ordered (RVWMO), main memory
kIo 2

Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O

When the Svpbmt extension is available, a page table entry's pbmt field

determines the physical memory type being accessed. Without that extension,

those bits must be all zero, which is also the PMA type (meaning the memory

type is controlled by the Physical Memory Attributes specification instead).

Defined at line 87 of file ../../zircon/kernel/lib/arch/include/lib/arch/riscv64/paging-traits.h

enum class Vendor
Name Value
kUnknown 0
kIntel 1
kAmd 2

Defined at line 89 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

enum class ArmGranuleSize
Name Value
k4KiB 12
k16KiB 14
k64KiB 16

[arm/v8]: D5.2.4 Memory translation granule size

Numeric value gives the base-2 logarithm of the size in bytes for

convenience in page-related arithmetic.

Defined at line 96 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum ArmSmcccReturnCode : uint32_t
Name Value
kArmSmcccSuccess 0
kArmSmcccNotSupported -1u
kArmSmcccNotRequired -2u
kArmSmcccInvalidParameter -3u

[arm/smccc] 7.1: Return Codes

These are the standard values for the Arm Architecture Calls' return

values in w0. Some calls return other values, hence this does not use

a scoped enum.

Defined at line 97 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

enum class Microarchitecture
Name Value Comments
kUnknown 0 --
kIntelCore2 1

Intel Core family (64-bit, display family 0x6).
kIntelNehalem 2

Intel Core family (64-bit, display family 0x6).
kIntelWestmere 3

Intel Core family (64-bit, display family 0x6).
kIntelSandyBridge 4

Intel Core family (64-bit, display family 0x6).
kIntelIvyBridge 5

Intel Core family (64-bit, display family 0x6).
kIntelHaswell 6

Intel Core family (64-bit, display family 0x6).
kIntelBroadwell 7

Intel Core family (64-bit, display family 0x6).
kIntelSkylake 8

Includes Kaby/Coffee/Whiskey/Amber/Comet Lake.
kIntelSkylakeServer 9

Includes Cascade/Cooper Lake.
kIntelCannonLake 10

A 10nm prototype only ever released on the Intel Core i3-8121U.
kIntelIceLake 11

A 10nm prototype only ever released on the Intel Core i3-8121U.
kIntelTigerLake 12

A 10nm prototype only ever released on the Intel Core i3-8121U.
kIntelAlderLake 13

A 10nm prototype only ever released on the Intel Core i3-8121U.
kIntelRaptorLake 14

A 10nm prototype only ever released on the Intel Core i3-8121U.
kIntelBonnell 15

Intel Atom family.
kIntelSaltwell 16

Intel Atom family.
kIntelSilvermont 17

Intel Atom family.
kIntelAirmont 18

Intel Atom family.
kIntelGoldmont 19

Intel Atom family.
kIntelGoldmontPlus 20

Intel Atom family.
kIntelTremont 21

Intel Atom family.
kAmdFamilyBulldozer 22

Bulldozer/Piledriver/Steamroller/Excavator.
kAmdFamilyJaguar 23

Jaguar.
kAmdFamilyZen 24

Zen 1, 1+, 2.
kAmdFamilyZen3 25

Zen 3, 4.

The list is not exhaustive and is in chronological order within groupings.

Microarchictectures that use the same processor (and, say, differ only in

performance or SoC composition) are regarded as equivalent.

Defined at line 98 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

enum class ArmAddressTranslationLevel
Name Value
kMinus1 0
k0 1
k1 2
k2 3
k3 4

[arm/v8]: D5.2 The VMSAv8-64 address translation system

Defined at line 118 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class ArmVirtualAddressRange
Name Value Comments
kLower 0

Configured by TCR_EL1.T0SZ.
kUpper 1

Configured by TCR_EL1.T1SZ.

Specifies the upper or lower virtual address range (i.e., the

1- or 0- extended ranges, respectively), which are configured separately.

Defined at line 142 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class ArmTcrTg0Value
Name Value
k4KiB 0b00
k16KiB 0b10
k64KiB 0b01

Granule size values for the TCR_EL1 and TCR_EL2 fields.

WARNING: The encodings for the TG0 field and TG1 field are different.

[arm/v8]: D13.2.120 TCR_EL1, Translation Control Register (EL1)

[arm/v8]: D13.2.121 TCR_EL2, Translation Control Register (EL2)

Defined at line 260 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/system.h

enum class ArmTcrTg1Value
Name Value
k4KiB 0b10
k16KiB 0b01
k64KiB 0b11

Defined at line 265 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/system.h

enum class ArmAddressTranslationAccessPermissions : uint8_t
Name Value Comments
kSupervisorReadWrite 0b00

EL1+ can read/write, EL0 no access.
kReadWrite 0b01

All levels can read/write.
kSupervisorReadOnly 0b10

EL1+ can read, EL0 no access.
kReadOnly 0b11

All levels can read.

[arm/v8]: Table D5-29 Data access permissions for stage 1 translations

Access permission for page table entries.

Defined at line 285 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class ArmAddressTranslationTableAccessPermissions : uint8_t
Name Value
kNoEffect 0b00
kNoEl0Access 0b01
kNoWriteAccess 0b10
kNoWriteOrEl0Access 0b11

Defined at line 292 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class ArmAddressTranslationDescriptorFormat : uint8_t
Name Value Comments
kBlock 0b0

Block descriptor for levels {0, 1, 2}. Invalid for level 3.
kTableOrPage 0b1

Table descriptor for levels {0, 1, 2}, page descriptor for level 3.

[arm/v8]: D5.3.1 VMSAv8-64 translation table level 0, level 1, and level 2

descriptor formats.

[arm/v8]: D5.3.2 Armv8 translation table level 3 descriptor formats

Defined at line 304 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

enum class X86CacheType : uint8_t
Name Value
kNull 0
kData 1
kInstruction 2
kUnified 3

---------------------------------------------------------------------------//

Leaf/Function 0x4.

[intel/vol2]: Table 3-8. Information Returned by CPUID Instruction.

[amd/vol3]: E.3.3 Functions 2h–4h—Reserved.

---------------------------------------------------------------------------//

Defined at line 321 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

enum class SpectreV2Mitigation
Name Value Comments
kIbrs 0

Enhanced/always-on IBRS (i.e., IBRS that can be enabled once without
automatic disabling) is preferred alone.
kIbpbRetpoline 1

IBPB and/or retpoline are recommended.
kIbpbRetpolineStibp 2

IBPB and/or retpoline are recommended - and STIPB, though not preferred as
a performant mitigation, is also present and may be used.

An architecturally prescribed mitigation for Spectre v2.

Defined at line 446 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

enum class ArmAsidSize
Name Value
k8bits 0b0000
k16bits 0b0010

ASID size.

Defined at line 486 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/feature.h

enum class ArmPhysicalAddressSize
Name Value Comments
k32Bits 0b0000 --
k36Bits 0b0001 --
k40Bits 0b0010 --
k42Bits 0b0011 --
k44Bits 0b0100 --
k48Bits 0b0101 --
k52Bits 0b0110 --
k56Bits 0b0111

FEAT_D128

Physical address size.

The same encoding is used by several registers, including system registers TCR_EL1.IPS,

TCR_EL2.PS, and the feature register ID_AA64MMFR0_EL1.PARange.

[arm/v9]: D24.2.82 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0

[arm/v9]: D24.2.182 Translation Control Register (EL1)

[arm/v9]: D24.2.183 Translation Control Register (EL2)

Defined at line 499 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/feature.h

enum class CpuidL2L3Associativity : uint8_t
Name Value Comments
kDisabled 0x0 --
kDirectMapped 0x1 --
k2Way 0x2 --
k3Way 0x3 --
k4Way 0x4 --
k6Way 0x5 --
k8Way 0x6 --
k16Way 0x8

0x7 is reserved.
kSeeLeaf0x8000001d 0x9

0x7 is reserved.
k32Way 0xa

0x7 is reserved.
k48Way 0xb

0x7 is reserved.
k64Way 0xc

0x7 is reserved.
k96Way 0xd

0x7 is reserved.
k128Way 0xe

0x7 is reserved.
kFullyAssociative 0xf

0x7 is reserved.

---------------------------------------------------------------------------//

Leaf/Function 0x8000'0006

[amd/vol3]: E.4.5 Function 8000_0006h—L2 Cache and TLB and L3 Cache Information.

---------------------------------------------------------------------------//

Defined at line 977 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

Records

Functions

  • void ArmDropToEl1WithoutEl2Monitor ()

    If we are executing at an exception level higher than EL1, this disables EL2

    monitoring, ensures would-be EL2 traps are routed to EL3, installs the

    current stack in SP_EL1 (if any), and then drops to EL1. If we are already

    at EL1, then this call is a no-op.

    This function is safe to call in any context. Care is taken to avoid using

    the stack and only uses scratch registers.

  • void LoadTaskRegister64 (SegmentSelector selector)

    Load the system Task Register.

    `selector` should be an index in the GDT containing a SystemSegmentDesc64 entry of type

    SegmentType::TSS_AVAILABLE.

    Defined at line 19 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • template <typename CpuidIoProvider>
    uint32_t GetApicId (CpuidIoProvider && io)

    Returns the APIC ID - x2APIC if supported - associated with the logical

    processor in turn associated with the provided CpuidIoProvider.

    Defined at line 19 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/apic-id.h

  • PagingConfiguration PagingConfigurationFromString (std::string_view name)

    Defined at line 23 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/paging-traits.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool SetX86CpuTurboState (CpuidIoProvider && cpuid, MsrIoProvider && msr, bool enable)

    Sets the "Turbo" state, which allows the processor to dynamically adjust and

    control its operating frequency. Turbo here collectively refers to the

    analogous technologies of "Intel Turbo Boost" and "AMD Turbo Core". Returns

    false if Turbo is unsupported; else returns true.

    For more detail, see:

    [intel/vol3]: 14.3.3 Intel® Turbo Boost Technology.

    [amd/vol2]: 17.2 Core Performance Boost.

    Defined at line 24 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/power.h

  • void LoadGdt (const GdtRegister64 & gdt)

    Load the x86-64 GDT register to the given value.

    Defined at line 29 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • void Yield ()

    Yield the processor momentarily. This should be used in busy waits.

    Defined at line 32 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

  • template <class Backtrace>
    size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

    The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

    provide container-like APIs for safely traversing a backtrace from either

    source using forward iteration.

    This stores a backtrace from either of those in a fixed-sized buffer, and

    returns the number of frames stored there. The optional third argument can

    be `__builtin_return_address(0)` in the function where the backtrace was

    collected. This will be included as the innermost frame if the backtrace

    doesn't already record it there, such as when the collecting function has

    no frame pointer itself.

    Defined at line 33 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

  • template <class Backtrace>
    size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

    The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

    provide container-like APIs for safely traversing a backtrace from either

    source using forward iteration.

    This stores a backtrace from either of those in a fixed-sized buffer, and

    returns the number of frames stored there. The optional third argument can

    be `__builtin_return_address(0)` in the function where the backtrace was

    collected. This will be included as the innermost frame if the backtrace

    doesn't already record it there, such as when the collecting function has

    no frame pointer itself.

    Defined at line 33 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

  • template <class Backtrace>
    size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

    The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

    provide container-like APIs for safely traversing a backtrace from either

    source using forward iteration.

    This stores a backtrace from either of those in a fixed-sized buffer, and

    returns the number of frames stored there. The optional third argument can

    be `__builtin_return_address(0)` in the function where the backtrace was

    collected. This will be included as the innermost frame if the backtrace

    doesn't already record it there, such as when the collecting function has

    no frame pointer itself.

    Defined at line 33 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

  • template <class Backtrace>
    size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

    The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

    provide container-like APIs for safely traversing a backtrace from either

    source using forward iteration.

    This stores a backtrace from either of those in a fixed-sized buffer, and

    returns the number of frames stored there. The optional third argument can

    be `__builtin_return_address(0)` in the function where the backtrace was

    collected. This will be included as the innermost frame if the backtrace

    doesn't already record it there, such as when the collecting function has

    no frame pointer itself.

    Defined at line 33 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

  • template <typename CpuidIoProvider>
    bool TsxIsSupported (CpuidIoProvider && cpuid)

    Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/extension.h

  • X86PagingLevelCount X86PagingLevelCountFromString (std::string_view name)

    Associates a conventional string name with each x86 paging configuration.

    Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

  • X86PagingLevelCount X86PagingLevelCountFromString (std::string_view name)

    Associates a conventional string name with each x86 paging configuration.

    Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

  • void DeviceMemoryBarrier ()

    Synchronize all memory accesses of all kinds.

    Defined at line 37 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

  • void LoadGdt (const AlignedGdtRegister64 & gdt)

    Defined at line 37 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • void ThreadMemoryBarrier ()

    Synchronize the ordering of all memory accesses wrt other CPUs.

    Defined at line 40 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

  • void LoadIdt (const GdtRegister64 & idt)

    Load the x86-64 IDT register to the given value.

    Defined at line 40 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool DisableTsx (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Attempts to disable TSX and returns whether it was successful.

    Defined at line 42 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/extension.h

  • void SerializeInstructions ()

    Force the processor to complete all modifications to register state and

    memory by previous instructions (including draining any buffered writes)

    before the next instruction is fetched.

    Defined at line 45 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

  • template <typename NopTraits
                            #if defined(__aarch64__)
                                      = Arm64NopTraits
                            #elif defined(__x86_64__) || defined(__i386__)
                                      = X86NopTraits>
    void NopFill (std::span<std::byte> instructions)

    Defined at line 46 of file ../../zircon/kernel/lib/arch/include/lib/arch/nop.h

  • template <typename NopTraits
                            #if defined(__aarch64__)
                                      = Arm64NopTraits
                            #elif defined(__x86_64__) || defined(__i386__)
                                      = X86NopTraits>
    void NopFill (std::span<std::byte> instructions)

    Defined at line 46 of file ../../zircon/kernel/lib/arch/include/lib/arch/nop.h

  • void LoadIdt (const AlignedGdtRegister64 & idt)

    Defined at line 47 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • bool X86InterruptHasErrorCode (arch::X86Interrupt vector)

    [intel/vol3]: 6.15 sections for each interrupt document whether it uses the

    error code. Most do not, so that's the presumption for the reserved slots.

    Defined at line 48 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/interrupt.h

  • ArmPagingConfiguration ArmPagingConfigurationFromString (std::string_view name)

    Associates a conventional string name with each arm64 paging configuration.

    Defined at line 53 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

  • uint64_t Cycles ()

    Return the current CPU cycle count.

    Defined at line 55 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

  • RiscvSatp::Mode RiscvSatpModeFromString (std::string_view name)

    Associates a conventional string name with each riscv64 paging configuration.

    Defined at line 56 of file ../../zircon/kernel/lib/arch/include/lib/arch/riscv64/paging-traits.h

  • void LoadLdt (SegmentSelector selector)

    Load the Local Descriptor Table Register (LDTR).

    `selector` can be null or a GDT selector for a valid ring 0 data segment.

    If the selector is valid, the base address and limit for the LDT are loaded

    from the GDT descriptor chosen by this selector. If the selector is null,

    the LDT is disabled.

    Defined at line 60 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • std::string_view ToString (Vendor vendor)

    Defined at line 60 of file ../../zircon/kernel/lib/arch/cpuid.cc

  • void DisableLdt ()

    Disable the LDT. Any future use of segment selectors with the LDT bit set

    produces an immediate #GP fault without examining any table in memory.

    Defined at line 66 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

  • std::string_view ToString (Microarchitecture microarch)

    Defined at line 72 of file ../../zircon/kernel/lib/arch/cpuid.cc

  • const char * X86InterruptName (arch::X86Interrupt vector)

    [intel/vol3]: 6.15 defines the two-letter "#" names for most of these.

    Defined at line 78 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/interrupt.h

  • template <typename CpuidIoProvider>
    bool HasIbpb (CpuidIoProvider && cpuid)

    Whether the Indirect Branch Prediction Barrier (IBPB) is supported.

    https://software.intel.com/security-software-guidance/deep-dives/deep-dive-indirect-branch-predictor-barrier.

    Defined at line 92 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • ArmSmcccReturnCode ArmSmcccGetReturnCode (uint64_t x0)

    This takes a 64-bit result in x0 and gets the 32-bit standard return code.

    Defined at line 105 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

  • template <typename TcrValueField>
    TcrValueField ArmGranuleSizeToTcr (arch::ArmGranuleSize granule)

    Convert from granule size to either arch::ArmTcrTg0Value or arch::ArmTcrTg1Value

    Defined at line 106 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    void IssueIbpb (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Issues an IBPB (Indirect Branch Prediction Barrier), which requires the

    feature to be supported.

    Defined at line 108 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • template <typename CpuidIoProvider>
    bool HasX86SwapgsBug (CpuidIoProvider && cpuid)

    Whether the CPU is susceptible to swapgs speculation attacks:

    https://software.intel.com/security-software-guidance/advisory-guidance/speculative-behavior-swapgs-and-segment-registers

    CVE-2019-1125.

    Defined at line 110 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasIbrs (CpuidIoProvider && cpuid, MsrIoProvider && msr, bool always_on_mode)

    Whether Indirect Branch Restricted Speculation (IBRS) is supported. The

    "always on" mode refers to an optimization in which IBRS need only be

    enabled once; IBRS in this mode are also referred to as "enhanced".

    https://software.intel.com/security-software-guidance/deep-dives/deep-dive-indirect-branch-restricted-speculation.

    Defined at line 119 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86MdsBugs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to any of the Microarchitectural Data

    Sampling (MDS) bugs.

    CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091.

    Defined at line 128 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    void EnableIbrs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Enables IBRS, which requires the feature to be supported.

    Defined at line 141 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • template <typename CpuidIoProvider>
    bool HasStibp (CpuidIoProvider && cpuid, bool always_on_mode)

    Whether Single Thread Indirect Branch Predictors (STIBP) are supported. The

    "always on" mode refers to an optimization in which STIBP need only be

    enabled once.

    https://software.intel.com/security-software-guidance/deep-dives/deep-dive-single-thread-indirect-branch-predictors.

    Defined at line 152 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • ArmSmcccVersion ArmSmcccVersionResult (uint64_t x0, ArmSmcccVersion not_supported)

    [arm/smccc] 7.2: SMCCC_VERSION

    This interprets the return value from SMCCC_VERSION or PSCI_VERSION.

    Defined at line 154 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

  • template <typename CpuidIoProvider>
    Vendor GetVendor (CpuidIoProvider && io)

    Defined at line 168 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    void EnableStibp (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Enables STIBP, which requires the feature to be supported.

    Defined at line 171 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86TaaBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to the TSX Asynchronous Abort (TAA) bug.

    CVE-2019-11135.

    Defined at line 172 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidValue>
    auto BootCpuid ()

    Convenient accessor for BootCpuidIo data, e.g.

    ```

    bool have_avx = arch::BootCpuid

    <arch

    ::CpuidFeatureFlagsC>().avx();

    ```

    Defined at line 186 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/boot-cpuid.h

  • template <typename CpuidValue>
    bool BootCpuidSupports ()

    Whether the leaf assosiated with a CPUID value type is supported, according

    to BootCpuidIo.

    Defined at line 193 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/boot-cpuid.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86MdsTaaBugs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to any of the MDS or TAA bugs, which are

    closely related and similarly mitigated.

    Defined at line 219 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider>
    Microarchitecture GetMicroarchitecture (CpuidIoProvider && io)

    Defined at line 221 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

  • template <typename CpuidIoProvider>
    bool CanMitigateX86MdsTaaBugs (CpuidIoProvider && cpuid)

    Whether the MDS/TAA bugs can be mitigated, which all make use of the same

    method (MD_CLEAR):

    https://software.intel.com/security-software-guidance/deep-dives/deep-dive-intel-analysis-microarchitectural-data-sampling#mitigation4processors

    Defined at line 227 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86SsbBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to the Speculative Store Bypass (SSB) bug:

    https://software.intel.com/security-software-guidance/advisory-guidance/speculative-store-bypass

    CVE-2018-3639.

    Defined at line 236 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • uintptr_t GetShadowCallStackPointer ()

    Defined at line 257 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

  • template <typename CpuidIoProvider>
    bool CanMitigateX86SsbBug (CpuidIoProvider && cpuid)

    Defined at line 327 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86MeltdownBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to the Rogue Data Cache Load (Meltdown) bug:

    https://software.intel.com/security-software-guidance/advisory-guidance/rogue-data-cache-load.

    CVE-2017-5754.

    Defined at line 338 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool HasX86L1tfBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Whether the CPU is susceptible to the L1 Terminal Fault (L1TF) bug:

    https://software.intel.com/security-software-guidance/advisory-guidance/l1-terminal-fault.

    CVE-2018-3615, CVE-2018-3620, CVE-2018-3646.

    Defined at line 396 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    SpectreV2Mitigation GetPreferredSpectreV2Mitigation (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Returns the preferred Spectre v2 mitigation strategy.

    Defined at line 461 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    void ApplyX86ErrataWorkarounds (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Applies workarounds to processor-specific errata.

    Defined at line 500 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • void LoadCodeSegmentSelector (SegmentSelector code_segment)

    Activate the given code selector and data selector.

    The two selectors should be indexes into the currently loaded GDT.

  • void InitializeBootCpuid ()

    Call this once early in startup, before any uses of arch::BootCpuIdIo. It

    initializes all the CpuidIo values in link map by using the CPUID

    instruction. See below for implementation details.

  • std::string_view ToString (X86CacheType type)

    Defined at line 260 of file ../../zircon/kernel/lib/arch/cpuid.cc

  • template <typename CpuidIoProvider, typename MsrIoProvider>
    bool MitigateX86SsbBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

    Attempt to mitigate the SSB bug. Return true if the bug was successfully

    mitigated.

    Defined at line 283 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

  • std::string_view ToString (MapError::Type type)

    Defined at line 321 of file ../../zircon/kernel/lib/arch/include/lib/arch/paging.h

  • template <typename CpuidValueTypetypename CpuidIoProvider>
    bool CpuidSupports (CpuidIoProvider && cpuid)

    Whether the leaf associated with a given CPUID value type is supported.

    Defined at line 1157 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

Concepts

template <typename T> IsOnStackApi std::default_initializable<T> && std::copyable<T> && requires (T is_on_stack, const CallFrame *fp) { { is_on_stack(fp) } -> std::convertible_to<_Bool>; }

The template parameter to FramePointerBacktrace is the type of a callable

object to determine whether it's safe to dereference a known-aligned pointer

that's expected to be on the stack. The type must be default-constructible

and copyable. But a non-default object can be passed to BackTrace().

Defined at line 96 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

Variables

const uint32_t kArmSmcccFunctionFast

Defined at line 41 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

const uint32_t kArmSmcccFunction64

Defined at line 46 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

const size_t kArmPsciRegisters

Defined at line 170 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 298 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelAddress

Defined at line 299 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelSize

Defined at line 302 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelSize

Defined at line 302 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h

const uintptr_t kAsmLabelSize

Defined at line 303 of file ../../zircon/kernel/lib/arch/include/lib/arch/asm.h