Namespaces

• namespace internal

• namespace testing

Enumerations

enum X86Interrupt

enum ArmL1ICachePolicy

enum RiscvFeature

enum ArmShareabilityAttribute

enum X86PagingLevelCount

enum ArmSmcccConduit

enum ArmPagingConfiguration

enum ArmCacheabilityAttribute

enum X86PagingLevel

enum ArmDeviceMemory

enum ArmSmcccFunction

enum X86Msr

enum VirtualAddressExtension

enum RiscvPagingLevel

enum ArmMaximumVirtualAddressWidth

enum RiscvMemoryType

enum Vendor

enum ArmGranuleSize

enum ArmSmcccReturnCode

enum Microarchitecture

enum ArmAddressTranslationLevel

enum ArmVirtualAddressRange

enum ArmTcrTg0Value

enum ArmTcrTg1Value

enum ArmAddressTranslationAccessPermissions

enum ArmAddressTranslationTableAccessPermissions

enum ArmAddressTranslationDescriptorFormat

enum X86CacheType

enum SpectreV2Mitigation

enum ArmAsidSize

enum ArmPhysicalAddressSize

enum CpuidL2L3Associativity

Records

• class AccessPermissions

• class AlignedGdtRegister64

• class AmdC0011028Msr

• class AmdC0011029Msr

• class AmdC001102dMsr

• class AmdHardwareConfigurationMsr

• class AmdLoadStoreConfigurationMsr

• class AmdVirtualSpeculationControlMsr

• class ApicIdDecoder

• class ArchCapabilitiesMsr

• class Arm64NopTraits

• class ArmAddressTranslationBlockDescriptor

• class ArmAddressTranslationDescriptor

• class ArmAddressTranslationPageDescriptor

• class ArmAddressTranslationTableDescriptor

• class ArmArchitecturalFeatureTrapRegister

• class ArmCacheTypeEl0

• class ArmCnthctlEl2

• class ArmCounterTimerHypervisorControl

• class ArmCptrEl2

• class ArmCptrEl3

• class ArmCurrentEl

• class ArmDaif

• class ArmDaifSetClr

• class ArmDataCacheZeroIdEl0

• class ArmElrEl1

• class ArmElrEl2

• class ArmElrEl3

• class ArmEsrEl1

• class ArmEsrEl2

• class ArmEsrEl3

• class ArmExceptionSyndromeRegister

• class ArmExtendedHypervisorConfigurationRegister

• class ArmHcrEl2

• class ArmHcrxEl2

• class ArmHypervisorConfigurationRegister

• class ArmIccSreEl1

• class ArmIccSreEl2

• class ArmIccSreEl3

• class ArmIdAa64IsaR0El1

• class ArmIdAa64IsaR1El1

• class ArmIdAa64IsaR2El1

• class ArmIdAa64Mmfr0El1

• class ArmIdAa64Mmfr1El1

• class ArmIdAa64Mmfr2El1

• class ArmIdAa64Mmfr3El1

• class ArmIdAa64Mmfr4El1

• class ArmIdAa64Pfr0El1

• class ArmIdAa64Pfr1El1

• class ArmInterruptControllerSystemRegisterEnableRegister

• class ArmMairEl1

• class ArmMairEl2

• class ArmMairNormalAttribute

• class ArmMemoryAttrIndirectionRegister

• class ArmMpidrEl1

• class ArmMultiprocessorAffinityRegister

• class ArmNzcv

• class ArmPagingTraits

• class ArmSavedProgramStatusRegister

• class ArmScrEl3

• class ArmSctlr2El1

• class ArmSctlr2El2

• class ArmSctlr2El3

• class ArmSctlrEl1

• class ArmSctlrEl2

• class ArmSctlrEl3

• class ArmSmcccVersion

• class ArmSpEl0

• class ArmSpEl1

• class ArmSpEl2

• class ArmSpsrEl1

• class ArmSpsrEl2

• class ArmSpsrEl3

• class ArmStackPointerRegister

• class ArmSystemControlRegister

• class ArmSystemControlRegister2

• class ArmSystemPagingState

• class ArmTcr2El1

• class ArmTcrEl1

• class ArmTcrEl2

• class ArmTranslationControlRegisterEl2Base

• class ArmTranslationTableBaseRegister

• class ArmTtbr0El1

• class ArmTtbr0El2

• class ArmTtbr0El3

• class ArmTtbr1El1

• class ArmTtbr1El2

• class ArmVbarEl1

• class ArmVbarEl2

• class ArmVbarEl3

• class ArmVectorBaseAddressRegister

• class ArmVectorExceptionLinkRegister

• class ArmVtcrEl2

• class ArmVttbrEl2

• class BootCpuidIo

• class CallFrame

• class CpuCacheInfo

• class CpuCacheLevelInfo

• class CpuidAddressSizeInfo

• class CpuidAdvancedPowerFeatureFlags

• class CpuidAmdFeatureFlagsC

• class CpuidAmdFeatureFlagsD

• class CpuidCacheTopologyA

• class CpuidCacheTopologyB

• class CpuidCacheTopologyC

• class CpuidCacheTopologyD

• class CpuidComputeUnitInfo

• class CpuidExtendedAmdFeatureFlagsB

• class CpuidExtendedApicId

• class CpuidExtendedFeatureFlagsB

• class CpuidExtendedFeatureFlagsC

• class CpuidExtendedFeatureFlagsD

• class CpuidExtendedSizeInfo

• class CpuidFeatureFlagsC

• class CpuidFeatureFlagsD

• class CpuidHypervisorNameB

• class CpuidHypervisorNameC

• class CpuidHypervisorNameD

• class CpuidIo

• class CpuidIoValue

• class CpuidIoValueBase

• class CpuidL1CacheInformation

• class CpuidL2CacheInformation

• class CpuidL3CacheInformation

• class CpuidMaximumExtendedLeaf

• class CpuidMaximumHypervisorLeaf

• class CpuidMaximumLeaf

• class CpuidMonitorMwaitA

• class CpuidMonitorMwaitB

• class CpuidMonitorMwaitC

• class CpuidMonitorMwaitD

• class CpuidNodeInfo

• class CpuidPerformanceMonitoringA

• class CpuidPerformanceMonitoringB

• class CpuidPerformanceMonitoringD

• class CpuidProcessorInfo

• class CpuidProcessorName2A

• class CpuidProcessorName2B

• class CpuidProcessorName2C

• class CpuidProcessorName2D

• class CpuidProcessorName3A

• class CpuidProcessorName3B

• class CpuidProcessorName3C

• class CpuidProcessorName3D

• class CpuidProcessorName4A

• class CpuidProcessorName4B

• class CpuidProcessorName4C

• class CpuidProcessorName4D

• class CpuidProcessorTraceMainB

• class CpuidProcessorTraceMainC

• class CpuidThermalAndPowerFeatureFlagsA

• class CpuidThermalAndPowerFeatureFlagsC

• class CpuidTopologyEnumerationA

• class CpuidTopologyEnumerationB

• class CpuidTopologyEnumerationC

• class CpuidTopologyEnumerationD

• class CpuidVendorB

• class CpuidVendorC

• class CpuidVendorD

• class CpuidVersionInfo

• class Desc32

• class EarlyTicks

• class ExamplePagingTraits

• class FramePointerBacktrace

• class GdtRegister64

• class GlobalCacheConsistencyContext

• class HypervisorName

• class MapError

• class MiscFeaturesMsr

• class Paging

• class PagingQueryResult

• class PredictionCommandMsr

• class ProcessorName

• class Random

• class Random

• class Random

• class RiscvFeatures

• class RiscvNopTraits

• class RiscvPagingTraits

• class RiscvPagingTraitsBase

• class RiscvSatp

• class RiscvScause

• class RiscvSstatus

• class RiscvStval

• class RiscvStvec

• class SegmentSelector

• class ShadowCallStackBacktrace

• class SpeculationControlMsr

• class SysReg

• class SysRegDerived

• class SysRegDerivedBase

• class SystemSegmentDesc64

• class TaskStateSegment64

• class TsxControlMsr

• class VirtualAddressBitRange

• class X86Cr0

• class X86Cr2

• class X86Cr3

• class X86Cr3PCID

• class X86Cr4

• class X86Cr8

• class X86ExtendedFeatureEnableRegisterMsr

• class X86InterruptFrame

• class X86MsrBase

• class X86NopTraits

• class X86PagingTraits

• class X86PagingTraitsBase

• class X86StandardSegments

• class X86Xcr0

Functions

• void ArmDropToEl1WithoutEl2Monitor ()

  If we are executing at an exception level higher than EL1, this disables EL2

  monitoring, ensures would-be EL2 traps are routed to EL3, installs the

  current stack in SP_EL1 (if any), and then drops to EL1. If we are already

  at EL1, then this call is a no-op.

  This function is safe to call in any context. Care is taken to avoid using

  the stack and only uses scratch registers.

• void LoadTaskRegister64 (SegmentSelector selector)

  Load the system Task Register.

  `selector` should be an index in the GDT containing a SystemSegmentDesc64 entry of type

  SegmentType::TSS_AVAILABLE.

  Defined at line 19 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• template <typename CpuidIoProvider>

  uint32_t GetApicId (CpuidIoProvider && io)

  Returns the APIC ID - x2APIC if supported - associated with the logical

  processor in turn associated with the provided CpuidIoProvider.

  Defined at line 19 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/apic-id.h

• PagingConfiguration PagingConfigurationFromString (std::string_view name)

  Defined at line 23 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/paging-traits.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool SetX86CpuTurboState (CpuidIoProvider && cpuid, MsrIoProvider && msr, bool enable)

  Sets the "Turbo" state, which allows the processor to dynamically adjust and

  control its operating frequency. Turbo here collectively refers to the

  analogous technologies of "Intel Turbo Boost" and "AMD Turbo Core". Returns

  false if Turbo is unsupported; else returns true.

  For more detail, see:

  [intel/vol3]: 14.3.3 Intel® Turbo Boost Technology.

  [amd/vol2]: 17.2 Core Performance Boost.

  Defined at line 24 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/power.h

• void LoadGdt (const GdtRegister64 & gdt)

  Load the x86-64 GDT register to the given value.

  Defined at line 29 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• void Yield ()

  Yield the processor momentarily. This should be used in busy waits.

  Defined at line 32 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

• template <class Backtrace>

  size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

  The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

  provide container-like APIs for safely traversing a backtrace from either

  source using forward iteration.

  This stores a backtrace from either of those in a fixed-sized buffer, and

  returns the number of frames stored there. The optional third argument can

  be `__builtin_return_address(0)` in the function where the backtrace was

  collected. This will be included as the innermost frame if the backtrace

  doesn't already record it there, such as when the collecting function has

  no frame pointer itself.

  Defined at line 32 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

• template <class Backtrace>

  size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

  The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

  provide container-like APIs for safely traversing a backtrace from either

  source using forward iteration.

  This stores a backtrace from either of those in a fixed-sized buffer, and

  returns the number of frames stored there. The optional third argument can

  be `__builtin_return_address(0)` in the function where the backtrace was

  collected. This will be included as the innermost frame if the backtrace

  doesn't already record it there, such as when the collecting function has

  no frame pointer itself.

  Defined at line 32 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

• template <class Backtrace>

  size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

  The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

  provide container-like APIs for safely traversing a backtrace from either

  source using forward iteration.

  This stores a backtrace from either of those in a fixed-sized buffer, and

  returns the number of frames stored there. The optional third argument can

  be `__builtin_return_address(0)` in the function where the backtrace was

  collected. This will be included as the innermost frame if the backtrace

  doesn't already record it there, such as when the collecting function has

  no frame pointer itself.

  Defined at line 32 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

• template <class Backtrace>

  size_t StoreBacktrace (Backtrace && bt, std::span<uintptr_t> pcs, void * raptr)

  The FramePointerBacktrace and ShadowCallStackBacktrace classes (see below)

  provide container-like APIs for safely traversing a backtrace from either

  source using forward iteration.

  This stores a backtrace from either of those in a fixed-sized buffer, and

  returns the number of frames stored there. The optional third argument can

  be `__builtin_return_address(0)` in the function where the backtrace was

  collected. This will be included as the innermost frame if the backtrace

  doesn't already record it there, such as when the collecting function has

  no frame pointer itself.

  Defined at line 32 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

• template <typename CpuidIoProvider>

  bool TsxIsSupported (CpuidIoProvider && cpuid)

  Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/extension.h

• X86PagingLevelCount X86PagingLevelCountFromString (std::string_view name)

  Associates a conventional string name with each x86 paging configuration.

  Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

• X86PagingLevelCount X86PagingLevelCountFromString (std::string_view name)

  Associates a conventional string name with each x86 paging configuration.

  Defined at line 34 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/paging-traits.h

• void DeviceMemoryBarrier ()

  Synchronize all memory accesses of all kinds.

  Defined at line 37 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

• void LoadGdt (const AlignedGdtRegister64 & gdt)

  Defined at line 37 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• void ThreadMemoryBarrier ()

  Synchronize the ordering of all memory accesses wrt other CPUs.

  Defined at line 40 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

• void LoadIdt (const GdtRegister64 & idt)

  Load the x86-64 IDT register to the given value.

  Defined at line 40 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool DisableTsx (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Attempts to disable TSX and returns whether it was successful.

  Defined at line 42 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/extension.h

• void SerializeInstructions ()

  Force the processor to complete all modifications to register state and

  memory by previous instructions (including draining any buffered writes)

  before the next instruction is fetched.

  Defined at line 45 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

• template <typename NopTraits
                              #if defined(__aarch64__)
                                        = Arm64NopTraits
                              #elif defined(__x86_64__) || defined(__i386__)
                                        = X86NopTraits>

  void NopFill (std::span<std::byte> instructions)

  Defined at line 46 of file ../../zircon/kernel/lib/arch/include/lib/arch/nop.h

• template <typename NopTraits
                              #if defined(__aarch64__)
                                        = Arm64NopTraits
                              #elif defined(__x86_64__) || defined(__i386__)
                                        = X86NopTraits>

  void NopFill (std::span<std::byte> instructions)

  Defined at line 46 of file ../../zircon/kernel/lib/arch/include/lib/arch/nop.h

• void LoadIdt (const AlignedGdtRegister64 & idt)

  Defined at line 47 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• bool X86InterruptHasErrorCode (arch::X86Interrupt vector)

  [intel/vol3]: 6.15 sections for each interrupt document whether it uses the

  error code. Most do not, so that's the presumption for the reserved slots.

  Defined at line 48 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/interrupt.h

• ArmPagingConfiguration ArmPagingConfigurationFromString (std::string_view name)

  Associates a conventional string name with each arm64 paging configuration.

  Defined at line 53 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

• uint64_t Cycles ()

  Return the current CPU cycle count.

  Defined at line 55 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/intrin.h

• RiscvSatp::Mode RiscvSatpModeFromString (std::string_view name)

  Associates a conventional string name with each riscv64 paging configuration.

  Defined at line 56 of file ../../zircon/kernel/lib/arch/include/lib/arch/riscv64/paging-traits.h

• void LoadLdt (SegmentSelector selector)

  Load the Local Descriptor Table Register (LDTR).

  `selector` can be null or a GDT selector for a valid ring 0 data segment.

  If the selector is valid, the base address and limit for the LDT are loaded

  from the GDT descriptor chosen by this selector. If the selector is null,

  the LDT is disabled.

  Defined at line 60 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• std::string_view ToString (Vendor vendor)

  Defined at line 60 of file ../../zircon/kernel/lib/arch/cpuid.cc

• void DisableLdt ()

  Disable the LDT. Any future use of segment selectors with the LDT bit set

  produces an immediate #GP fault without examining any table in memory.

  Defined at line 66 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/descriptor-regs.h

• std::string_view ToString (Microarchitecture microarch)

  Defined at line 72 of file ../../zircon/kernel/lib/arch/cpuid.cc

• const char * X86InterruptName (arch::X86Interrupt vector)

  [intel/vol3]: 6.15 defines the two-letter "#" names for most of these.

  Defined at line 78 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/interrupt.h

• template <typename CpuidIoProvider>

  bool HasIbpb (CpuidIoProvider && cpuid)

  Whether the Indirect Branch Prediction Barrier (IBPB) is supported.

  https://software.intel.com/security-software-guidance/deep-dives/deep-dive-indirect-branch-predictor-barrier.

  Defined at line 92 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• ArmSmcccReturnCode ArmSmcccGetReturnCode (uint64_t x0)

  This takes a 64-bit result in x0 and gets the 32-bit standard return code.

  Defined at line 105 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

• template <typename TcrValueField>

  TcrValueField ArmGranuleSizeToTcr (arch::ArmGranuleSize granule)

  Convert from granule size to either arch::ArmTcrTg0Value or arch::ArmTcrTg1Value

  Defined at line 106 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/paging-traits.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  void IssueIbpb (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Issues an IBPB (Indirect Branch Prediction Barrier), which requires the

  feature to be supported.

  Defined at line 108 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• template <typename CpuidIoProvider>

  bool HasX86SwapgsBug (CpuidIoProvider && cpuid)

  Whether the CPU is susceptible to swapgs speculation attacks:

  https://software.intel.com/security-software-guidance/advisory-guidance/speculative-behavior-swapgs-and-segment-registers

  CVE-2019-1125.

  Defined at line 110 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasIbrs (CpuidIoProvider && cpuid, MsrIoProvider && msr, bool always_on_mode)

  Whether Indirect Branch Restricted Speculation (IBRS) is supported. The

  "always on" mode refers to an optimization in which IBRS need only be

  enabled once; IBRS in this mode are also referred to as "enhanced".

  https://software.intel.com/security-software-guidance/deep-dives/deep-dive-indirect-branch-restricted-speculation.

  Defined at line 119 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86MdsBugs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to any of the Microarchitectural Data

  Sampling (MDS) bugs.

  CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091.

  Defined at line 128 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  void EnableIbrs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Enables IBRS, which requires the feature to be supported.

  Defined at line 141 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• template <typename CpuidIoProvider>

  bool HasStibp (CpuidIoProvider && cpuid, bool always_on_mode)

  Whether Single Thread Indirect Branch Predictors (STIBP) are supported. The

  "always on" mode refers to an optimization in which STIBP need only be

  enabled once.

  https://software.intel.com/security-software-guidance/deep-dives/deep-dive-single-thread-indirect-branch-predictors.

  Defined at line 152 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• ArmSmcccVersion ArmSmcccVersionResult (uint64_t x0, ArmSmcccVersion not_supported)

  [arm/smccc] 7.2: SMCCC_VERSION

  This interprets the return value from SMCCC_VERSION or PSCI_VERSION.

  Defined at line 154 of file ../../zircon/kernel/lib/arch/include/lib/arch/arm64/smccc.h

• template <typename CpuidIoProvider>

  Vendor GetVendor (CpuidIoProvider && io)

  Defined at line 168 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  void EnableStibp (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Enables STIBP, which requires the feature to be supported.

  Defined at line 171 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/speculation.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86TaaBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to the TSX Asynchronous Abort (TAA) bug.

  CVE-2019-11135.

  Defined at line 172 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidValue>

  auto BootCpuid ()

  Convenient accessor for BootCpuidIo data, e.g.

  ```

  bool have_avx = arch::BootCpuid

  <arch

  ::CpuidFeatureFlagsC>().avx();

  ```

  Defined at line 186 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/boot-cpuid.h

• template <typename CpuidValue>

  bool BootCpuidSupports ()

  Whether the leaf assosiated with a CPUID value type is supported, according

  to BootCpuidIo.

  Defined at line 193 of file ../../zircon/kernel/lib/arch/x86/include/lib/arch/x86/boot-cpuid.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86MdsTaaBugs (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to any of the MDS or TAA bugs, which are

  closely related and similarly mitigated.

  Defined at line 219 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider>

  Microarchitecture GetMicroarchitecture (CpuidIoProvider && io)

  Defined at line 221 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

• template <typename CpuidIoProvider>

  bool CanMitigateX86MdsTaaBugs (CpuidIoProvider && cpuid)

  Whether the MDS/TAA bugs can be mitigated, which all make use of the same

  method (MD_CLEAR):

  https://software.intel.com/security-software-guidance/deep-dives/deep-dive-intel-analysis-microarchitectural-data-sampling#mitigation4processors

  Defined at line 227 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• uintptr_t GetShadowCallStackPointer ()

  Defined at line 235 of file ../../zircon/kernel/lib/arch/include/lib/arch/backtrace.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86SsbBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to the Speculative Store Bypass (SSB) bug:

  https://software.intel.com/security-software-guidance/advisory-guidance/speculative-store-bypass

  CVE-2018-3639.

  Defined at line 236 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider>

  bool CanMitigateX86SsbBug (CpuidIoProvider && cpuid)

  Defined at line 327 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86MeltdownBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to the Rogue Data Cache Load (Meltdown) bug:

  https://software.intel.com/security-software-guidance/advisory-guidance/rogue-data-cache-load.

  CVE-2017-5754.

  Defined at line 338 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool HasX86L1tfBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Whether the CPU is susceptible to the L1 Terminal Fault (L1TF) bug:

  https://software.intel.com/security-software-guidance/advisory-guidance/l1-terminal-fault.

  CVE-2018-3615, CVE-2018-3620, CVE-2018-3646.

  Defined at line 396 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  SpectreV2Mitigation GetPreferredSpectreV2Mitigation (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Returns the preferred Spectre v2 mitigation strategy.

  Defined at line 461 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• template <typename CpuidIoProvider, typename MsrIoProvider>

  void ApplyX86ErrataWorkarounds (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Applies workarounds to processor-specific errata.

  Defined at line 500 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• void LoadCodeSegmentSelector (SegmentSelector code_segment)

  Activate the given code selector and data selector.

  The two selectors should be indexes into the currently loaded GDT.

• void InitializeBootCpuid ()

  Call this once early in startup, before any uses of arch::BootCpuIdIo. It

  initializes all the CpuidIo values in link map by using the CPUID

  instruction. See below for implementation details.

• std::string_view ToString (X86CacheType type)

  Defined at line 260 of file ../../zircon/kernel/lib/arch/cpuid.cc

• template <typename CpuidIoProvider, typename MsrIoProvider>

  bool MitigateX86SsbBug (CpuidIoProvider && cpuid, MsrIoProvider && msr)

  Attempt to mitigate the SSB bug. Return true if the bug was successfully

  mitigated.

  Defined at line 283 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/bug.h

• std::string_view ToString (MapError::Type type)

  Defined at line 321 of file ../../zircon/kernel/lib/arch/include/lib/arch/paging.h

• template <typename CpuidValueTypetypename CpuidIoProvider>

  bool CpuidSupports (CpuidIoProvider && cpuid)

  Whether the leaf associated with a given CPUID value type is supported.

  Defined at line 1157 of file ../../zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h

Variables

const uint32_t kArmSmcccFunctionFast

const uint32_t kArmSmcccFunction64

const size_t kArmPsciRegisters

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelAddress

const uintptr_t kAsmLabelSize

const uintptr_t kAsmLabelSize

const uintptr_t kAsmLabelSize