class HdmiEncoderVerticalSyncStartOddFields

Defined at line 1208 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

ENCP_DVI_VSO_BLINE_ODD (DVI/HDMI Vsync out start line for odd field)

S912 Datasheet, Section 27.5 "CVBS and LCD", page 392.

Public Members

 field_RsvdZ_1218

 field_lines_1228

hwreg::RegisterAddr<HdmiEncoderVerticalSyncStartOddFields> Get ()

Defined at line 1211 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >

typename SelfType::ValueType lines ()

Start line (inclusive) of the vertical sync signal for each field, in

lines.

S912 datasheet only specifies bits 10-0 are used for this field. However,

experiments confirm that bit 11 is functional on S912 and SoCs with similar

encoder designs (S905D2, S905D3, A311D) due to their support for the

3840x2160 resolution. Therefore, this code utilizes bits 11-0 for the

field.

Defined at line 1228 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >

SelfType & set_lines (typename SelfType::ValueType val)