class VideoInputChannelFifoControl3

Defined at line 270 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

VDIN0_ASFIFO_CTRL3, VDIN1_ASFIFO_CTRL3

A311D Datasheet, Section 10.2.3.42 VDIN, Pages 1106, 1128.

S905D2 Datasheet, Section 7.2.3.41 VDIN, Pages 798-799, 822.

S905D3 Datasheet, Section 8.2.3.42 VDIN, Pages 733, 755.

Public Members

 field_channel8_data_enabled_292

 field_channel8_go_field_signal_enabled_295

 field_channel8_go_line_signal_enabled_298

 field_channel8_input_vsync_is_negative_301

 field_channel8_input_hsync_is_negative_304

 field_channel8_async_fifo_software_reset_on_vsync_307

 field_channel8_clear_fifo_overflow_bit_311

 field_channel8_async_fifo_software_reset_317

 field_channel6_data_enabled_324

 field_channel6_go_field_signal_enabled_327

 field_channel6_go_line_signal_enabled_330

 field_channel6_input_vsync_is_negative_333

 field_channel6_input_hsync_is_negative_336

 field_channel6_async_fifo_software_reset_on_vsync_339

 field_channel6_clear_fifo_overflow_bit_343

 field_channel6_async_fifo_software_reset_349

Public Methods

hwreg::RegisterAddr<VideoInputChannelFifoControl3> Get (VideoInputModuleId video_input)

Defined at line 273 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_data_enabled ()

Enable data transmission on channel 8.

Defined at line 292 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_data_enabled (typename SelfType::ValueType val)

Enable data transmission on channel 8.

Defined at line 292 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_go_field_signal_enabled ()

Enable go_field (Vsync) signals on channel 8.

Defined at line 295 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_go_field_signal_enabled (typename SelfType::ValueType val)

Enable go_field (Vsync) signals on channel 8.

Defined at line 295 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_go_line_signal_enabled ()

Enable go_line (Hsync) signals for channel 8.

Defined at line 298 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_go_line_signal_enabled (typename SelfType::ValueType val)

Enable go_line (Hsync) signals for channel 8.

Defined at line 298 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_input_vsync_is_negative ()

True iff the input video on channel 8 has negative polarity Vsync signals.

Defined at line 301 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_input_vsync_is_negative (typename SelfType::ValueType val)

True iff the input video on channel 8 has negative polarity Vsync signals.

Defined at line 301 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_input_hsync_is_negative ()

True iff the input video on channel 6 has negative polarity Hsync signals.

Defined at line 304 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_input_hsync_is_negative (typename SelfType::ValueType val)

True iff the input video on channel 6 has negative polarity Hsync signals.

Defined at line 304 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_async_fifo_software_reset_on_vsync ()

If true, the ASFIFO will be reset on each Vsync signal.

Defined at line 307 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_async_fifo_software_reset_on_vsync (typename SelfType::ValueType val)

If true, the ASFIFO will be reset on each Vsync signal.

Defined at line 307 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_clear_fifo_overflow_bit ()

Clears (and acknowledges) the `vdi8_fifo_overflow` bit in the

`VDIN0/1_COM_STATUS2` register.

Defined at line 311 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_clear_fifo_overflow_bit (typename SelfType::ValueType val)

Clears (and acknowledges) the `vdi8_fifo_overflow` bit in the

`VDIN0/1_COM_STATUS2` register.

Defined at line 311 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel8_async_fifo_software_reset ()

Resets the async FIFO.

This bit is a "level signal" bit. Drivers reset the FIFO by first setting

it to 1, and then to 0.

Defined at line 317 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel8_async_fifo_software_reset (typename SelfType::ValueType val)

Resets the async FIFO.

This bit is a "level signal" bit. Drivers reset the FIFO by first setting

it to 1, and then to 0.

Defined at line 317 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_data_enabled ()

Enable data transmission on channel 6.

Defined at line 324 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_data_enabled (typename SelfType::ValueType val)

Enable data transmission on channel 6.

Defined at line 324 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_go_field_signal_enabled ()

Enable go_field (Vsync) signals on channel 6.

Defined at line 327 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_go_field_signal_enabled (typename SelfType::ValueType val)

Enable go_field (Vsync) signals on channel 6.

Defined at line 327 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_go_line_signal_enabled ()

Enable go_line (Hsync) signals on channel 6.

Defined at line 330 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_go_line_signal_enabled (typename SelfType::ValueType val)

Enable go_line (Hsync) signals on channel 6.

Defined at line 330 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_input_vsync_is_negative ()

True iff the input video on channel 6 has negative polarity Vsync signals.

Defined at line 333 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_input_vsync_is_negative (typename SelfType::ValueType val)

True iff the input video on channel 6 has negative polarity Vsync signals.

Defined at line 333 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_input_hsync_is_negative ()

True iff the input video on channel 6 has negative polarity Hsync signals.

Defined at line 336 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_input_hsync_is_negative (typename SelfType::ValueType val)

True iff the input video on channel 6 has negative polarity Hsync signals.

Defined at line 336 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_async_fifo_software_reset_on_vsync ()

If true, the channel ASFIFO will be reset on each Vsync signal.

Defined at line 339 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_async_fifo_software_reset_on_vsync (typename SelfType::ValueType val)

If true, the channel ASFIFO will be reset on each Vsync signal.

Defined at line 339 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_clear_fifo_overflow_bit ()

Clears (and acknowledges) the `vdi6_fifo_overflow` bit in the

`VDIN0/1_COM_STATUS2` register.

Defined at line 343 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_clear_fifo_overflow_bit (typename SelfType::ValueType val)

Clears (and acknowledges) the `vdi6_fifo_overflow` bit in the

`VDIN0/1_COM_STATUS2` register.

Defined at line 343 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

typename SelfType::ValueType channel6_async_fifo_software_reset ()

Resets the async FIFO.

This bit is a "level signal" bit. Drivers reset the FIFO by first setting

it to 1, and then to 0.

Defined at line 349 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h

template <, >

SelfType & set_channel6_async_fifo_software_reset (typename SelfType::ValueType val)

Resets the async FIFO.

This bit is a "level signal" bit. Drivers reset the FIFO by first setting

it to 1, and then to 0.

Defined at line 349 of file ../../src/graphics/display/drivers/amlogic-display/video-input-regs.h