class HdmiEncoderModeConfig

Defined at line 216 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

ENCP_VIDEO_MODE

S912 Datasheet, Section 27.5 "CVBS and LCD", pages 380-381.

Public Members

 field_RsvdZ_228
 field_debug_counter_enabled_234
 field_display_enabled_signal_polarity_236
 field_horizontal_period_increases_by_one_240
 field_is_output_interlaced_248
 field_vertical_sync_offset_for_odd_field_enabled_252
 field_vertical_active_on_for_odd_field_enabled_256
 field_analog_equalizing_pulse_for_odd_field_enabled_276
 field_analog_equalizing_pulse_enabled_281
 field_bit7_undocumented_287
 field_analog_hsync_and_equalizing_pulse_switch_in_center_292
 field_analog_vertical_sync_for_odd_field_enabled_296
 field_second_vertical_sync_in_a_line_enabled_300
 field_analog_vertical_sync_end_for_odd_field_aligned_to_half_line_318
 field_analog_vertical_sync_start_for_odd_field_aligned_to_half_line_322
 field_analog_vertical_sync_end_for_even_field_aligned_to_half_line_326
 field_analog_vertical_sync_start_for_even_field_aligned_to_half_line_330

Public Methods

hwreg::RegisterAddr<HdmiEncoderModeConfig> Get ()

Defined at line 223 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType debug_counter_enabled ()

If true, the ENCP encoder debug counter registers are enabled.

Documented as "pixel count and line count shadow enable" in the S912

datasheet.

Defined at line 234 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_debug_counter_enabled (typename SelfType::ValueType val)

If true, the ENCP encoder debug counter registers are enabled.

Documented as "pixel count and line count shadow enable" in the S912

datasheet.

Defined at line 234 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
DisplayEnabledSignalPolarity display_enabled_signal_polarity ()

Defined at line 236 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_display_enabled_signal_polarity (DisplayEnabledSignalPolarity val)

Defined at line 236 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType horizontal_period_increases_by_one ()

If true, the encoder increases the value of the horizontal period (maximum

pixel counter) register by one internally.

Defined at line 240 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_horizontal_period_increases_by_one (typename SelfType::ValueType val)

If true, the encoder increases the value of the horizontal period (maximum

pixel counter) register by one internally.

Defined at line 240 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType is_output_interlaced ()

Bits 12-0 configure the timing signals for the interlaced output.

Rather than directly manipulating these bits, it's preferred to use the

helper methods: ConfigureFor1080i(), ConfigureForHighDefinitionProgressive()

and ConfigureForStandardDefinitionProgressive().

Defined at line 248 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_is_output_interlaced (typename SelfType::ValueType val)

Bits 12-0 configure the timing signals for the interlaced output.

Rather than directly manipulating these bits, it's preferred to use the

helper methods: ConfigureFor1080i(), ConfigureForHighDefinitionProgressive()

and ConfigureForStandardDefinitionProgressive().

Defined at line 248 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_vertical_sync_offset_for_odd_field_enabled (typename SelfType::ValueType val)

True iff the Vertical Sync Offset for odd field registers are enabled to

produce vertical sync signals for odd fields.

Defined at line 252 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType vertical_sync_offset_for_odd_field_enabled ()

True iff the Vertical Sync Offset for odd field registers are enabled to

produce vertical sync signals for odd fields.

Defined at line 252 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_vertical_active_on_for_odd_field_enabled (typename SelfType::ValueType val)

True iff the Vertical Active On for odd field registers are enabled to

produce video signals for odd fields.

Defined at line 256 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType vertical_active_on_for_odd_field_enabled ()

True iff the Vertical Active On for odd field registers are enabled to

produce video signals for odd fields.

Defined at line 256 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_equalizing_pulse_for_odd_field_enabled ()

True iff the equalizing pulse generator is enabled to produce analog

equalizing pulse signals for odd fields in interlaced outputs.

Defined at line 276 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_equalizing_pulse_for_odd_field_enabled (typename SelfType::ValueType val)

True iff the equalizing pulse generator is enabled to produce analog

equalizing pulse signals for odd fields in interlaced outputs.

Defined at line 276 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_equalizing_pulse_enabled ()

True iff the equalizing pulse generator is enabled to produce analog

equalizing pulse signals for even fields in interlaced outputs, or for

progressive outputs.

Defined at line 281 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_equalizing_pulse_enabled (typename SelfType::ValueType val)

True iff the equalizing pulse generator is enabled to produce analog

equalizing pulse signals for even fields in interlaced outputs, or for

progressive outputs.

Defined at line 281 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType bit7_undocumented ()

Undocumented in the S912 datasheet.

The S912 datasheet requires this bit set to 1 for 1080i output, and

requires this bit set to 0 for 720p, 480p and 540p output.

Defined at line 287 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_bit7_undocumented (typename SelfType::ValueType val)

Undocumented in the S912 datasheet.

The S912 datasheet requires this bit set to 1 for 1080i output, and

requires this bit set to 0 for 720p, 480p and 540p output.

Defined at line 287 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_hsync_and_equalizing_pulse_switch_in_center ()

Documented as "Enable Hsync and equalization pulse switch in center" in

the S912 datasheet. The function of this bit is unclear; it seems it

only works for the analog signal output.

Defined at line 292 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_hsync_and_equalizing_pulse_switch_in_center (typename SelfType::ValueType val)

Documented as "Enable Hsync and equalization pulse switch in center" in

the S912 datasheet. The function of this bit is unclear; it seems it

only works for the analog signal output.

Defined at line 292 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_vertical_sync_for_odd_field_enabled ()

True iff the Analog vertical sync signal generator is enabled to produce

analog Vsync signals for odd fields.

Defined at line 296 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_vertical_sync_for_odd_field_enabled (typename SelfType::ValueType val)

True iff the Analog vertical sync signal generator is enabled to produce

analog Vsync signals for odd fields.

Defined at line 296 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType second_vertical_sync_in_a_line_enabled ()

Documented as "Enable 2nd vertical pulse in a line (1080i)" in the

S912 datasheet. The function of this bit is unclear.

Defined at line 300 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_second_vertical_sync_in_a_line_enabled (typename SelfType::ValueType val)

Documented as "Enable 2nd vertical pulse in a line (1080i)" in the

S912 datasheet. The function of this bit is unclear.

Defined at line 300 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_vertical_sync_end_for_odd_field_aligned_to_half_line ()

True iff the end of the vertical sync is aligned to the half of a line

for odd fields.

Defined at line 318 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_vertical_sync_end_for_odd_field_aligned_to_half_line (typename SelfType::ValueType val)

True iff the end of the vertical sync is aligned to the half of a line

for odd fields.

Defined at line 318 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_vertical_sync_start_for_odd_field_aligned_to_half_line ()

True iff the start of the vertical sync is aligned to the half of a line

for odd fields.

Defined at line 322 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_vertical_sync_start_for_odd_field_aligned_to_half_line (typename SelfType::ValueType val)

True iff the start of the vertical sync is aligned to the half of a line

for odd fields.

Defined at line 322 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_vertical_sync_end_for_even_field_aligned_to_half_line ()

True iff the end of the vertical sync is aligned to the half of a line

for even fields.

Defined at line 326 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_vertical_sync_end_for_even_field_aligned_to_half_line (typename SelfType::ValueType val)

True iff the end of the vertical sync is aligned to the half of a line

for even fields.

Defined at line 326 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
typename SelfType::ValueType analog_vertical_sync_start_for_even_field_aligned_to_half_line ()

True iff the start of the vertical sync is aligned to the half of a line

for even fields.

Defined at line 330 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

template <, >
SelfType & set_analog_vertical_sync_start_for_even_field_aligned_to_half_line (typename SelfType::ValueType val)

True iff the start of the vertical sync is aligned to the half of a line

for even fields.

Defined at line 330 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

HdmiEncoderModeConfig & ConfigureFor1080i ()

The following register field configuration matches the preferred register

value provided in the S912 datasheet.

Defined at line 334 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

HdmiEncoderModeConfig & ConfigureForHighDefinitionProgressive ()

The following register field configuration matches the preferred register

value provided in the Amlogic-provided code (except for the DE signal

polarity, which the drivers should set by themselves for consistency with

the transmitter configuration).

The datasheets and the Amlogic-provided code deviate in some register field

configurations: The S912 datasheet mentions that the register should be

set to 0x140 for 720p, while the Amlogic-provided code use 0x4040 for all

progressive outputs.

Defined at line 359 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

HdmiEncoderModeConfig & ConfigureForStandardDefinitionProgressive ()

The following register field configuration matches the preferred register

value provided in the S912 datasheet for 480p or 576p.

Defined at line 377 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

Enumerations

enum DisplayEnabledSignalPolarity
Name Value
kActiveLow 0
kActiveHigh 1

Defined at line 218 of file ../../src/graphics/display/drivers/amlogic-display/encoder-regs.h

Records