class VideoClock1Control

Defined at line 336 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

HHI_VID_CLK_CNTL

A311D Datasheet, Section 8.7.6 Register Descriptions, Page 151.

S905D2 Datasheet, Section 6.6.6 Register Descriptions, Page 137.

S905D3 Datasheet, Section 6.7.6 Register Descriptions, Page 129-130.

Public Members

 field_timing_controller_clock_control_352

 field_divider1_enabled_358

 field_divider0_enabled_364

 field_mux_source_366

 field_soft_reset_371

 field_lcd_analog_clock_mux_enabled_374

 field_lcd_analog_clock_selection_380

 field_RsvdZ_382

 field_div12_enabled_384

 field_div6_enabled_385

 field_div4_enabled_386

 field_div2_enabled_387

 field_div1_enabled_388

Public Methods

hwreg::RegisterAddr<VideoClock1Control> Get ()

Defined at line 343 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_timing_controller_clock_control (typename SelfType::ValueType val)

Bits 31-21 control the clock generation module for timing controller clock

(cts_tcon). The subfield definition is not in the register description

table but is mentioned in the clock tree diagram.

A311D Datasheet, Section 8.7.1 Clock Trees, Page 114.

S905D2 Datasheet, Section 6.6.2 Clock Trees, Page 98.

S905D3 Datasheet, Section 6.7.2 Clock Trees, Page 99.

Defined at line 352 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType timing_controller_clock_control ()

Bits 31-21 control the clock generation module for timing controller clock

(cts_tcon). The subfield definition is not in the register description

table but is mentioned in the clock tree diagram.

A311D Datasheet, Section 8.7.1 Clock Trees, Page 114.

S905D2 Datasheet, Section 6.6.2 Clock Trees, Page 98.

S905D3 Datasheet, Section 6.7.2 Clock Trees, Page 99.

Defined at line 352 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider1_enabled ()

If false, the output signal of divider /N1 is gated.

Divider /N1 works iff `divider1_enabled` and the `dividers_enabled`

field in `VideoClock1Divider` register are both true.

Defined at line 358 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider1_enabled (typename SelfType::ValueType val)

If false, the output signal of divider /N1 is gated.

Divider /N1 works iff `divider1_enabled` and the `dividers_enabled`

field in `VideoClock1Divider` register are both true.

Defined at line 358 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider0_enabled ()

If false, the output signal of divider /N0 is gated.

Divider /N0 works iff `divider0_enabled` and the `dividers_enabled`

field in `VideoClock1Divider` register are both true.

Defined at line 364 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider0_enabled (typename SelfType::ValueType val)

If false, the output signal of divider /N0 is gated.

Divider /N0 works iff `divider0_enabled` and the `dividers_enabled`

field in `VideoClock1Divider` register are both true.

Defined at line 364 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

VideoClockMuxSource mux_source ()

Defined at line 366 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_mux_source (VideoClockMuxSource val)

Defined at line 366 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_soft_reset (typename SelfType::ValueType val)

This is a "level triggered" signal. Drivers reset the clock dividers by

first setting the bit to 1, sleeping for 10 us (empirical value from VIM3

using A311D chip) and then setting the bit to 0.

Defined at line 371 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType soft_reset ()

This is a "level triggered" signal. Drivers reset the clock dividers by

first setting the bit to 1, sleeping for 10 us (empirical value from VIM3

using A311D chip) and then setting the bit to 0.

Defined at line 371 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType lcd_analog_clock_mux_enabled ()

Enables the mux for the clock "lcd_an_clk_ph2" and "lcd_an_clk_ph3".

Defined at line 374 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_lcd_analog_clock_mux_enabled (typename SelfType::ValueType val)

Enables the mux for the clock "lcd_an_clk_ph2" and "lcd_an_clk_ph3".

Defined at line 374 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

LcdAnalogClockSelection lcd_analog_clock_selection ()

"Video Clock Tree" diagrams use the bit 11 on register 0x1a

(HHI_GP1_PLL_CNTL2) which doesn't match the register definitions on the

same datasheet. Experiments on VIM3 (Amlogic A311D) shows that this bit

is the correct bit to select input source for LCD analog clocks.

Defined at line 380 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_lcd_analog_clock_selection (LcdAnalogClockSelection val)

"Video Clock Tree" diagrams use the bit 11 on register 0x1a

(HHI_GP1_PLL_CNTL2) which doesn't match the register definitions on the

same datasheet. Experiments on VIM3 (Amlogic A311D) shows that this bit

is the correct bit to select input source for LCD analog clocks.

Defined at line 380 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType div12_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 384 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_div12_enabled (typename SelfType::ValueType val)

Defined at line 384 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType div6_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 385 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_div6_enabled (typename SelfType::ValueType val)

Defined at line 385 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType div4_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 386 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_div4_enabled (typename SelfType::ValueType val)

Defined at line 386 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType div2_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 387 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_div2_enabled (typename SelfType::ValueType val)

Defined at line 387 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType div1_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 388 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_div1_enabled (typename SelfType::ValueType val)

Defined at line 388 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

Enumerations

enum LcdAnalogClockSelection

Name	Value
kVideoClock1Div6	0
kVideoClock1Div12	1

Defined at line 338 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h