class VpuClockBControl

Defined at line 817 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

HHI_VPU_CLKB_CNTL - Configures the "cts_vpu_clkb" and "cts_vpu_clkb_tmp"

clock signals.

The VPU Clock B (cts_vpu_clkb) first selects its source from a mux with

VPU clock and 500, 400, 285.7 MHz fixed clocks, and then gets divided by

divider 1 and divider 2.

The datasheets describe it as two clock signals: the target clock signal

"cts_vpu_clkb", and a temporary clock signal ("cts_vpu_clkb_tmp").

"cts_vpu_clkb_tmp" takes inputs from PLLs, and "cts_vpu_clkb" takes inputs

from only "cts_vpu_clkb_tmp", and clock has its own divider. Since the

temporary clock signal is not used anywhere else, this is equivalent to our

two-divider model described above.

A311D Datasheet, Section 8.7.1.4 "EE Clock Tree", row "cts_vpu_clkb" and

"cts_vpu_clkb_tmp", Page 113; Section 8.7.6 Register Descriptions,

Page 164.

S905D2 Datasheet, Section 6.7.1.4 "EE Clock Tree", row "cts_vpu_clkb" and

"cts_vpu_clkb_tmp", Page 97; Section 6.6.6 Register Descriptions, Page 141.

S905D3 Datasheet, Section 6.7.2.4 "EE Clock Tree", row "cts_vpu_clkb" and

"cts_vpu_clkb_tmp", Page 98; Section 6.7.6 Register Descriptions, Page 136.

Public Members

 field_RsvdZ_837

 field_divider1_enabled_841

 field_clock_source_843

 field_divider1_minus_one_846

 field_effective_after_vpu_clkb_pulse_850

 field_divider2_enabled_854

 field_divider2_minus_one_857

static const int kMinDivider1

static const int kMaxDivider1

static const int kMinDivider2

static const int kMaxDivider2

Public Methods

hwreg::RegisterAddr<VpuClockBControl> Get ()

Defined at line 835 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider1_enabled ()

The clock is enabled only when both `divider1_enabled` and

`divider2_enabled` are true.

Defined at line 841 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider1_enabled (typename SelfType::ValueType val)

The clock is enabled only when both `divider1_enabled` and

`divider2_enabled` are true.

Defined at line 841 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

ClockSource clock_source ()

Defined at line 843 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_clock_source (ClockSource val)

Defined at line 843 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider1_minus_one ()

Prefer `Divider1()` and `SetDivider1()` to accessing the field directly.

Defined at line 846 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider1_minus_one (typename SelfType::ValueType val)

Prefer `Divider1()` and `SetDivider1()` to accessing the field directly.

Defined at line 846 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType effective_after_vpu_clkb_pulse ()

Iff true, latches the register write until the next vpu_clkb_pulse signal.

Defined at line 850 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_effective_after_vpu_clkb_pulse (typename SelfType::ValueType val)

Iff true, latches the register write until the next vpu_clkb_pulse signal.

Defined at line 850 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider2_enabled ()

The clock is enabled only when both `divider1_enabled` and

`divider2_enabled` are true.

Defined at line 854 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider2_enabled (typename SelfType::ValueType val)

The clock is enabled only when both `divider1_enabled` and

`divider2_enabled` are true.

Defined at line 854 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

typename SelfType::ValueType divider2_minus_one ()

Prefer `Divider2()` and `SetDivider2()` to accessing the field directly.

Defined at line 857 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

template <, >

SelfType & set_divider2_minus_one (typename SelfType::ValueType val)

Prefer `Divider2()` and `SetDivider2()` to accessing the field directly.

Defined at line 857 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

VpuClockBControl & SetDivider1 (int divider1)

Defined at line 860 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

int Divider1 ()

Defined at line 866 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

VpuClockBControl & SetDivider2 (int divider2)

Defined at line 868 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

int Divider2 ()

Defined at line 874 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h

Enumerations

enum ClockSource

Name	Value
kVpuClock	0
kFixed500Mhz	1
kFixed400Mhz	2
kFixed285_7Mhz	3

In the S905D3 datasheet, the mapping between selection values and clock

sources are not mentioned in the register description table, but only in

the EE Clock tree table, which matches the rest of the definitions.

Defined at line 822 of file ../../src/graphics/display/drivers/amlogic-display/clock-regs.h