class HdmiPllControl0

Defined at line 67 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HHI_HDMI_PLL_CNTL0 - HDMI PLL Control Register 0.

A311D Datasheet, Section 8.7.2.8 "HDMI PLL", Page 120;

Section 8.7.6 "Register Descriptions", Page 178.

S905D2 Datasheet, Section 6.6.3.7 "HDMI PLL", Page 104;

Section 6.6.6 "Register Descriptions", Page 164.

S905D3 Datasheet, Section 6.7.6 "Register Descriptions", Page 150.

Public Members

 field_is_locked_85

 field_is_locked_a_89

 field_reset_94

 field_pll_enabled_95

 field_numerator_fraction_enabled_100

 field_RsvdZ_106

 field_hdmi_clock_out2_enabled_109

 field_hdmi_clock_out_enabled_112

 field_RsvdZ_118

 field_output_divider3_selection_124

 field_output_divider2_selection_130

 field_output_divider1_selection_136

 field_RsvdZ_142

 field_denominator_150

 field_RsvdZ_158

 field_numerator_integer_181

static const int kMinAllowedDenominator

static const int kMaxAllowedDenominator

static const int kMinAllowedNumeratorInteger

static const int kMaxAllowedNumeratorInteger

Public Methods

hwreg::RegisterAddr<HdmiPllControl0> Get ()

Defined at line 81 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType is_locked ()

Read-only. From Amlogic-provided code, the PLL is considered locked iff

`is_locked` and `is_locked_a` are both true.

Defined at line 85 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_is_locked (typename SelfType::ValueType val)

Read-only. From Amlogic-provided code, the PLL is considered locked iff

`is_locked` and `is_locked_a` are both true.

Defined at line 85 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType is_locked_a ()

Read-only. From Amlogic-provided code, the PLL is considered locked iff

`is_locked` and `is_locked_a` are both true.

Defined at line 89 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_is_locked_a (typename SelfType::ValueType val)

Read-only. From Amlogic-provided code, the PLL is considered locked iff

`is_locked` and `is_locked_a` are both true.

Defined at line 89 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType reset ()

Resets the PLL. Per Amlogic-provided code, to reset / reconfigure the PLL,

drivers set this bit to 1, then set PLL control registers, and finally

set it to 0 and wait for the PLL to lock.

Defined at line 94 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_reset (typename SelfType::ValueType val)

Resets the PLL. Per Amlogic-provided code, to reset / reconfigure the PLL,

drivers set this bit to 1, then set PLL control registers, and finally

set it to 0 and wait for the PLL to lock.

Defined at line 94 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType pll_enabled ()

NOLINTEND(misc-non-private-member-variables-in-classes)

Defined at line 95 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_pll_enabled (typename SelfType::ValueType val)

Defined at line 95 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType numerator_fraction_enabled ()

Bit 27 is not defined in any of the Amlogic datasheets.

Amlogic-provided code indicates that this bit is set true iff the

fractional part of the numerator is non-zero.

Defined at line 100 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_numerator_fraction_enabled (typename SelfType::ValueType val)

Bit 27 is not defined in any of the Amlogic datasheets.

Amlogic-provided code indicates that this bit is set true iff the

fractional part of the numerator is non-zero.

Defined at line 100 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType hdmi_clock_out2_enabled ()

Gate-controls the "HDMI_CLK_OUT2" signal.

Defined at line 109 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_hdmi_clock_out2_enabled (typename SelfType::ValueType val)

Gate-controls the "HDMI_CLK_OUT2" signal.

Defined at line 109 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType hdmi_clock_out_enabled ()

Gate-controls the "HDMI_CLK_OUT" signal.

Defined at line 112 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_hdmi_clock_out_enabled (typename SelfType::ValueType val)

Gate-controls the "HDMI_CLK_OUT" signal.

Defined at line 112 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

OutputDividerSelection output_divider3_selection ()

Known as "HDMI_DPLL_OD2<1:0>" in the datasheet.

It's preferred to use `OutputDivider3()` and `SetOutputDivider3()` to

direct field manipulation.

Defined at line 124 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_output_divider3_selection (OutputDividerSelection val)

Known as "HDMI_DPLL_OD2<1:0>" in the datasheet.

It's preferred to use `OutputDivider3()` and `SetOutputDivider3()` to

direct field manipulation.

Defined at line 124 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

OutputDividerSelection output_divider2_selection ()

Known as "HDMI_DPLL_OD<3:2>" in the datasheet.

It's preferred to use `OutputDivider2()` and `SetOutputDivider2()` to

direct field manipulation.

Defined at line 130 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_output_divider2_selection (OutputDividerSelection val)

Known as "HDMI_DPLL_OD<3:2>" in the datasheet.

It's preferred to use `OutputDivider2()` and `SetOutputDivider2()` to

direct field manipulation.

Defined at line 130 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

OutputDividerSelection output_divider1_selection ()

Known as "HDMI_DPLL_OD<1:0>" in the datasheet.

It's preferred to use `OutputDivider1()` and `SetOutputDivider1()` to

direct field manipulation.

Defined at line 136 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_output_divider1_selection (OutputDividerSelection val)

Known as "HDMI_DPLL_OD<1:0>" in the datasheet.

It's preferred to use `OutputDivider1()` and `SetOutputDivider1()` to

direct field manipulation.

Defined at line 136 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType denominator ()

The actual value of the denominator.

Amlogic-provided code requires this value be one on all Fuchsia-supported

platforms (A311D, S905D2, S905D3, and T931).

It's preferred to use `SetDenomiator()` to direct field manipulation.

Defined at line 150 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_denominator (typename SelfType::ValueType val)

The actual value of the denominator.

Amlogic-provided code requires this value be one on all Fuchsia-supported

platforms (A311D, S905D2, S905D3, and T931).

It's preferred to use `SetDenomiator()` to direct field manipulation.

Defined at line 150 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

typename SelfType::ValueType numerator_integer ()

The actual value of the integral part of the numerator.

Amlogic-provided code requires this value be in the range [2, 511] on all

Fuchsia-supported platforms (A311D, S905D2, S905D3, and T931). However,

the datasheet mentions that this field only uses bit 7-0, so this field

must not exceed 255.

Also note that on all Fuchsia-supported platforms, the crystal oscillator

is fixed to 24MHz, and the frequency of the HDMI PLL VCO cannot exceed

6GHz; so in this specific case, the maximum allowed `numerator_integer`

should be

6000 / 24 + 2 = 251

when `numerator_fraction`

= -1.

Given all the constraints above, for maximum convenience, compatibility and

extensibility (to use other oscillators), we keep the original bit

definition of the field (bits 7-0), and require the value must be in the

range of [2, 255]. Drivers must check that the final VCO frequency does

not exceed the 6GHz hardware limit.

It's preferred to use `SetNumeratorInteger()` to direct field manipulation.

Defined at line 181 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

template <, >

SelfType & set_numerator_integer (typename SelfType::ValueType val)

The actual value of the integral part of the numerator.

Amlogic-provided code requires this value be in the range [2, 511] on all

Fuchsia-supported platforms (A311D, S905D2, S905D3, and T931). However,

the datasheet mentions that this field only uses bit 7-0, so this field

must not exceed 255.

Also note that on all Fuchsia-supported platforms, the crystal oscillator

is fixed to 24MHz, and the frequency of the HDMI PLL VCO cannot exceed

6GHz; so in this specific case, the maximum allowed `numerator_integer`

should be

6000 / 24 + 2 = 251

when `numerator_fraction`

= -1.

Given all the constraints above, for maximum convenience, compatibility and

extensibility (to use other oscillators), we keep the original bit

definition of the field (bits 7-0), and require the value must be in the

range of [2, 255]. Drivers must check that the final VCO frequency does

not exceed the 6GHz hardware limit.

It's preferred to use `SetNumeratorInteger()` to direct field manipulation.

Defined at line 181 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

int OutputDivider3 ()

Defined at line 185 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HdmiPllControl0 & SetOutputDivider3 (int divider)

Defined at line 199 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

int OutputDivider2 ()

Defined at line 212 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HdmiPllControl0 & SetOutputDivider2 (int divider)

Defined at line 226 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

int OutputDivider1 ()

Defined at line 239 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HdmiPllControl0 & SetOutputDivider1 (int divider)

Defined at line 253 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HdmiPllControl0 & SetDenominator (int denominator)

Defined at line 266 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

HdmiPllControl0 & SetNumeratorInteger (int numerator_integer)

Defined at line 274 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h

Enumerations

enum OutputDividerSelection

Name	Value
k1	0
k2	1
k4	2

Values are from the following table:

A311D Datasheet, Section 8.7.2.8 "HDMI PLL", Table 6-13 "A311D HDMI PLL OD

Control Table", Page 120.

S905D2 Datasheet, Section 6.6.3.7 "HDMI PLL", Table 6-13 "S905D2 HDMI PLL

OD Control Table", Page 104;

Defined at line 75 of file ../../src/graphics/display/drivers/amlogic-display/pll-regs.h