starnix_core/arch/x64/
task.rs

1// Copyright 2023 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5use crate::task::PageFaultExceptionReport;
6use starnix_uapi::signals::{SIGFPE, SIGSEGV, Signal};
7
8pub fn decode_page_fault_exception_report(
9    data: &zx::ExceptionArchData,
10) -> PageFaultExceptionReport {
11    // [intel/vol3]: 6.15: Interrupt 14--Page-Fault Exception (#PF)
12    let faulting_address = data.cr2;
13    let not_present = data.err_code & 0x01 == 0; // Low bit means "present"
14    let is_write = data.err_code & 0x02 != 0;
15    let is_execute = data.err_code & 0xF0 != 0;
16
17    PageFaultExceptionReport { faulting_address, not_present, is_write, is_execute }
18}
19
20pub fn get_signal_for_general_exception(data: &zx::ExceptionArchData) -> Option<Signal> {
21    // See Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3, Chapter 6
22    // (Interrupt and exception handling).
23    match data.vector {
24        // 0: Division by 0.
25        // 16: FPU exception.
26        // 19: SSE exception.
27        0 | 16 | 19 => Some(SIGFPE),
28
29        // General Protection Fault, e.g. `hlt` instruction.
30        13 => Some(SIGSEGV),
31
32        _ => None,
33    }
34}
starnix_core/arch/x64/task.rs

starnix_core/arch/x64/
task.rs
