libarch/x86/
system.rs

1// Copyright 2026 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5use bitrs::layout;
6use regio::x86::Cr;
7
8/// [intel/vol3]: 2.5 Control Registers: CR0
9pub const CR0: Cr<0, ControlRegister0> = Cr::new();
10
11layout!({
12    /// The layout of [`CR0`].
13    pub struct ControlRegister0(u64);
14    {
15        let __ @ 63..32 = 0;
16        let pg @ 31; // Paging enabled
17        let cd @ 30; // Cache disabled
18        let nw @ 29; // Not write-through
19        // Bits [28:19] are reserved.
20        let __ @ 28..19;
21        let am @ 18; // Alignment mask (support alignment checking)
22        // Bit 17 is reserved.
23        let __ @ 17;
24        let wp @ 16; // Write protect (prevent supervisor writing to RO pages)
25        // Bits [15:6] are reserved.
26        let __ @ 15..6;
27        let ne @ 5; // Numeric error (control FPU exceptions)
28        let et @ 4; // Extension type (reserved on modern CPUs, always 1)
29        let ts @ 3; // Task switched (trap on FPU/MMX/SSE/etc reg access)
30        let em @ 2; // Emulation (trap on FPU/MMX/SSE/etc instructions)
31        let mp @ 1; // Monitor Coprocessor
32        let pe @ 0; // Protection Enable (enable protected mode)
33    }
34});
35
36// There is no CR1.
37
38/// [intel/vol3]: 2.5 Control Registers: CR2
39pub const CR2: Cr<2, ControlRegister2> = Cr::new();
40
41layout!({
42    /// The layout of [`CR2`].
43    pub struct ControlRegister2(u64);
44    {
45        let address @ 63..0;
46    }
47});
48
49/// [intel/vol3]: 2.5 Control Registers: CR3 without PCID feature
50pub const CR3: Cr<3, ControlRegister3> = Cr::new();
51
52/// [intel/vol3]: 2.5 Control Registers: CR3 with CR4.PCIDE enabled
53pub const CR3_PCID: Cr<3, ControlRegister3Pcid> = Cr::new();
54
55layout!({
56    /// The layout of [`CR3`].
57    pub struct ControlRegister3(u64);
58    {
59        let __ @ 63..52;
60        #[unshifted]
61        let base @ 51..12; // 4k-aligned physical byte address.
62
63        // Bits [12:5] and [2:0] are reserved and ignored, but "assumed to be zero".
64        // In case of future additions it's probably best to write them back as
65        // written rather than RSVDZ them.
66        let __ @ 11..5;
67        let pcd @ 4; // Page-level Cache Disable
68        let pwt @ 3; // Page-level Write-Through
69        let __ @ 2..0;
70    }
71});
72
73layout!({
74    /// The layout of [`CR3_PCID`].
75    pub struct ControlRegister3Pcid(u64);
76    {
77        let noflush @ 63; // When this bit is set upon load, do not flush the PCID's TLB.
78        let __ @ 62..52;
79        #[unshifted]
80        let base @ 51..12; // 4k-aligned physical byte address.
81        let pcid @ 11..0; // 12 bit PCID associated with this mmu context
82    }
83});
84
85/// [intel/vol3]: 2.5 Control Registers: CR4
86pub const CR4: Cr<4, ControlRegister4> = Cr::new();
87
88layout!({
89    /// The layout of [`CR4`].
90    pub struct ControlRegister4(u64);
91    {
92        let __ @ 63..32 = 0;
93        let __ @ 31..25;
94        let pks @ 24; // Enable protection keys for supervisor-mode pages
95        let cet @ 23; // Control-flow Enforcement Technology
96        let pke @ 22; // Enable protection keys for user-mode pages
97        let smap @ 21; // SMAP-Enable Bit
98        let smep @ 20; // SMEP-Enable Bit
99        let __ @ 19;
100        let osxsave @ 18; // XSAVE and Processor Extended States-Enable Bit
101        let pcide @ 17; // PCID-Enable Bit
102        let fsgsbase @ 16; // FSGSBASE-Enable Bit
103        let __ @ 15;
104        let smxe @ 14; // SMX-Enable Bit
105        let vmxe @ 13; // VMX-Enable Bit
106        let la57 @ 12; // 57-bit linear addresses
107        let umip @ 11; // User-Mode Instruction Prevention
108        let osmmexcpt @ 10; // OS supports unmasked SIMD FP Exceptions
109        let osfxsr @ 9; // OS supports FXSAVE and FXRSTOR
110        let pce @ 8; // Performance-Monitoring Counter Enable
111        let pge @ 7; // Page Global Enable
112        let mce @ 6; // Machine-Check Enable
113        let pae @ 5; // Physical Address Extension
114        let pse @ 4; // Page Size Extensions
115        let de @ 3; // Debugging Extensions
116        let tsd @ 2; // Time Stamp Disable
117        let pvi @ 1; // Protected-Mode Virtual Interrupts
118        let vme @ 0; // Virtual-8086 Mode Extensions
119    }
120});
121
122// There is no CR5, CR6, or CR7.
123
124/// [intel/vol3]: 2.5 Control Registers: CR8
125pub const CR8: Cr<8, ControlRegister8> = Cr::new();
126
127layout!({
128    /// The layout of [`CR8`].
129    pub struct ControlRegister8(u64);
130    {
131        let __ @ 63..4;
132        let tpl @ 3..0; // Task Priority Level
133    }
134});
135
136layout!({
137    /// [intel/vol3]: 2.6 Extended Control Registers
138    ///
139    /// The layout of extended control register 0 (XCR0).
140    pub struct ExtendedControlRegister0(u64);
141    {
142        // Bit 63 of XCR0 is reserved for future expansion and will not represent a
143        // processor state component.
144        let __ @ 63 = 0;
145        let __ @ 62..10 = 0; // Reserved for future expansion.
146        let pkru @ 9;
147        let __ @ 8 = 0;
148        let hi16_zmm @ 7;
149        let zmm_hi256 @ 6;
150        let opmask @ 5;
151        let bndcsr @ 4;
152        let bndreg @ 3;
153        let avx @ 2;
154        let sse @ 1;
155        let x87 @ 0;
156    }
157});
libarch/x86/system.rs

libarch/x86/
system.rs
