libarch/x86/
feature.rs

1// Copyright 2026 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5use bitrs::layout;
6use regio::x86::{Cpuid, Msr};
7use regio::{Ro, RwSafe};
8
9use super::Vendor;
10use super::cpuid::EXTENDED_FEATURES_D;
11
12/// [intel/vol4]: Table 2-2.  IA-32 Architectural MSRs (Contd.).
13///
14/// Enumerates general archicturectural features.
15pub const IA32_ARCH_CAPABILITIES: Msr<0x0000_010a, ArchCapabilitiesMsr, Ro> = Msr::new();
16
17layout!({
18    /// Layout for [`IA32_ARCH_CAPABILITIES`].
19    pub struct ArchCapabilitiesMsr(u64);
20    {
21        let __ @ 63..9;
22        let taa_no @ 8;
23        let tsx_ctrl @ 7;
24        let if_pschange_mc_no @ 6;
25        let mds_no @ 5;
26        let ssb_no @ 4;
27        let skip_l1dfl_vmentry @ 3;
28        let rsba @ 2;
29        let ibrs_all @ 1;
30        let rdcl_no @ 0;
31    }
32});
33
34impl ArchCapabilitiesMsr {
35    pub fn is_supported(cpuid: impl Cpuid) -> bool {
36        cpuid.read(EXTENDED_FEATURES_D).ia32_arch_capabilities()
37    }
38}
39
40/// [intel/vol4]: Table 2-3.  MSRs in Processors Based on Intel® Core™ Microarchitecture.
41///
42/// Enables miscellaenous processor features.
43pub const IA32_MISC_ENABLE: Msr<0x0000_01a0, MiscFeaturesMsr, RwSafe> = Msr::new();
44
45layout!({
46    /// Layout for [`IA32_MISC_ENABLE`].
47    pub struct MiscFeaturesMsr(u64);
48    {
49        let __ @ 63..40;
50        let ip_prefetch_disable @ 39;
51        let ida_disable @ 38;
52        let dcu_prefetch_disable @ 37;
53        let __ @ 36..35;
54        let xd_bit_disable @ 34;
55        let __ @ 33..24;
56        let xtpr_message_disable @ 23;
57        let limit_cpuid_maxval @ 22;
58        let __ @ 21;
59        let eist_select_lock @ 20;
60        let adjacent_cache_line_prefetch_disable @ 19;
61        let monitor_fsm @ 18;
62        let __ @ 17;
63        let eist @ 16;
64        let __ @ 15..14;
65        let tm2 @ 13;
66        let pebs_unavailable @ 12;
67        let bts_unavailable @ 11;
68        let ferr_mux @ 10;
69        let hardware_prefetch_disable @ 9;
70        let __ @ 8;
71        let perf_mon_available @ 7;
72        let __ @ 6..4;
73        let automatic_thermal_control_circuit @ 3;
74        let __ @ 2..1;
75        let fast_strings @ 0;
76    }
77});
78
79impl MiscFeaturesMsr {
80    pub fn is_supported(vendor: Vendor) -> bool {
81        vendor == Vendor::Intel
82    }
83}
84
85/// [amd/ppr/17h/01h,08h]:  2.1.14.2 MSRs - MSRC000_0xxx.
86///
87/// AMD hardware configuration.
88pub const MSRC001_0015: Msr<0xc001_0015, AmdHardwareConfigurationMsr, RwSafe> = Msr::new();
89
90layout!({
91    /// Layout for [`MSRC001_0015`].
92    pub struct AmdHardwareConfigurationMsr(u64);
93    {
94        let __ @ 63..31;
95        let ir_perf_en @ 30;
96        let __ @ 29..28;
97        let eff_freq_read_only_lock @ 27;
98        let eff_frq_cnt_mwait @ 26;
99        let cpb_dis @ 25;
100        let tsc_freq_sel @ 24;
101        let __ @ 23..22;
102        let lock_tsc_to_current_p0 @ 21;
103        let io_cfg_gp_fault @ 20;
104        let __ @ 19;
105        let mc_status_wr_en @ 18;
106        let wrap32_dis @ 17;
107        let __ @ 16..15;
108        let rsm_sp_cyc_dis @ 14;
109        let smi_sp_cyc_dis @ 13;
110        let __ @ 12..11;
111        let mon_mwait_user_en @ 10;
112        let mon_mwait_dis @ 9;
113        let ignne_em @ 8;
114        let allow_ferr_on_ne @ 7;
115        let __ @ 6..5;
116        let invdwbinvd @ 4;
117        let tlb_cache_dis @ 3;
118        let __ @ 2..1;
119        let smm_lock @ 0;
120    }
121});
122
123/// [intel/vol3]: 2.2.1 Extended Feature Enable Register
124/// [amd/vol2]: 3.1.7 Extended Feature Enable Register (EFER)
125pub const IA32_EFER: Msr<0xc000_0080, X86ExtendedFeatureEnableRegisterMsr, RwSafe> = Msr::new();
126
127layout!({
128    /// Layout for [`IA32_EFER`].
129    pub struct X86ExtendedFeatureEnableRegisterMsr(u64);
130    {
131        // Bits [18:12] are reserved in Intel docs, but further specified by AMD.
132        // AMD documents the reserved bits among [63:9] as MBZ while Intel simply
133        // says "reserved".
134        let __ @ 63..19 = 0;
135        let mcommit @ 17; // (AMD only) Enable mcommit instruction.
136        let __ @ 16 = 0; // Reserved, MBZ in AMD.
137        let tce @ 15; // (AMD only) Translation Cache Extension.
138        let ffxsr @ 14; // (AMD only) Fast fxsave/fxrstor.
139        let lmsle @ 13; // (AMD only) Long Mode Segment Limit Enable
140        let svme @ 12; // (AMD only) Secure Virtual Machine Enable
141        let nxe @ 11; // Enable non-execute bit in page tables.
142        let lma @ 10; // IA-32e (x86-64) mode active.
143        let __ @ 9 = 0; // Reserved, MBZ in AMD.
144        let lme @ 8; // IA-32e (x86-64) mode enable.
145        // Bits [7:1] are reserved.  AMD documents them as R(ead)A(s)Z(ero) while
146        // Intel simply says "reserved".
147        let __ @ 7..1 = 0;
148        let sce @ 0; // Enable syscall/sysret instructions.
149    }
150});
libarch/x86/feature.rs

libarch/x86/
feature.rs
