libarch/x86/
extension.rs

1// Copyright 2026 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5use bitrs::layout;
6use regio::RwSafe;
7use regio::traits::{ReadReg, RwSafeReg};
8use regio::x86::{Cpuid, Msr};
9
10use super::ArchCapabilitiesMsr;
11use super::cpuid::EXTENDED_FEATURES_B;
12
13/// [intel/vol4]: Table 2-2.  IA-32 Architectural MSRs (Contd.).
14///
15/// TSX (Transactional Synchronization Extension) controls.
16pub const IA32_TSX_CTRL: Msr<0x0000_0122, TsxControlMsr, RwSafe> = Msr::new();
17
18layout!({
19    /// Layout for [`IA32_TSX_CTRL`].
20    pub struct TsxControlMsr(u64);
21    {
22        let __ @ 63..2;
23        let rtm_disable @ 1;
24        let tsx_cpuid_clear @ 0;
25    }
26});
27
28impl TsxControlMsr {
29    fn is_supported(cpuid: impl Cpuid, msr: impl ReadReg<ArchCapabilitiesMsr>) -> bool {
30        ArchCapabilitiesMsr::is_supported(cpuid) && msr.read().tsx_ctrl()
31    }
32}
33
34pub fn tsx_is_supported(cpuid: impl Cpuid) -> bool {
35    // [intel/vol3]: 18.3.6.5     Performance Monitoring and Intel® TSX.
36    let features = cpuid.read(EXTENDED_FEATURES_B);
37    features.hle() || features.rtm()
38}
39
40/// Attempts to disable TSX and returns whether it was successful.
41pub fn disable_tsx(
42    cpuid: impl Cpuid,
43    arch_capabilities_msr: impl ReadReg<ArchCapabilitiesMsr>,
44    tsx_control_msr: impl RwSafeReg<TsxControlMsr>,
45) -> bool {
46    if !TsxControlMsr::is_supported(&cpuid, &arch_capabilities_msr) {
47        return false;
48    }
49
50    tsx_control_msr.modify(|val| {
51        val.set_rtm_disable(true).set_tsx_cpuid_clear(true);
52    });
53
54    true
55}
libarch/x86/extension.rs

libarch/x86/
extension.rs
