1#![warn(clippy::all)]
3#![allow(unused_parens, unused_variables, unused_mut, unused_imports, unreachable_code)]
4
5pub mod natural {
6
7 pub use fidl_next_common_fuchsia_hardware_spiimpl::natural::*;
8
9 #[derive(Debug, PartialEq)]
10 pub struct SpiImplRegisterVmoRequest {
11 pub chip_select: u32,
12
13 pub vmo_id: u32,
14
15 pub vmo: ::fidl_next_fuchsia_mem::natural::Range,
16
17 pub rights: ::fidl_next_fuchsia_hardware_sharedmemory::natural::SharedVmoRight,
18 }
19
20 unsafe impl<___E> ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>
21 for SpiImplRegisterVmoRequest
22 where
23 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
24 ___E: ::fidl_next::fuchsia::HandleEncoder,
25 {
26 #[inline]
27 fn encode(
28 self,
29 encoder_: &mut ___E,
30 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplRegisterVmoRequest>,
31 _: (),
32 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
33 ::fidl_next::munge! {
34 let crate::wire::SpiImplRegisterVmoRequest {
35 chip_select,
36 vmo_id,
37 vmo,
38 rights,
39
40 } = out_;
41 }
42
43 ::fidl_next::Encode::encode(self.chip_select, encoder_, chip_select, ())?;
44
45 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(chip_select.as_mut_ptr()) };
46
47 ::fidl_next::Encode::encode(self.vmo_id, encoder_, vmo_id, ())?;
48
49 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo_id.as_mut_ptr()) };
50
51 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
52
53 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo.as_mut_ptr()) };
54
55 ::fidl_next::Encode::encode(self.rights, encoder_, rights, ())?;
56
57 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(rights.as_mut_ptr()) };
58
59 Ok(())
60 }
61 }
62
63 unsafe impl<___E>
64 ::fidl_next::EncodeOption<
65 ::fidl_next::wire::Box<'static, crate::wire::SpiImplRegisterVmoRequest>,
66 ___E,
67 > for SpiImplRegisterVmoRequest
68 where
69 ___E: ::fidl_next::Encoder + ?Sized,
70 SpiImplRegisterVmoRequest:
71 ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>,
72 {
73 #[inline]
74 fn encode_option(
75 this: ::core::option::Option<Self>,
76 encoder: &mut ___E,
77 out: &mut ::core::mem::MaybeUninit<
78 ::fidl_next::wire::Box<'static, crate::wire::SpiImplRegisterVmoRequest>,
79 >,
80 _: (),
81 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
82 if let Some(inner) = this {
83 ::fidl_next::EncoderExt::encode_next(encoder, inner)?;
84 ::fidl_next::wire::Box::encode_present(out);
85 } else {
86 ::fidl_next::wire::Box::encode_absent(out);
87 }
88
89 Ok(())
90 }
91 }
92
93 impl ::fidl_next::FromWire<crate::wire::SpiImplRegisterVmoRequest> for SpiImplRegisterVmoRequest {
94 #[inline]
95 fn from_wire(wire: crate::wire::SpiImplRegisterVmoRequest) -> Self {
96 Self {
97 chip_select: ::fidl_next::FromWire::from_wire(wire.chip_select),
98
99 vmo_id: ::fidl_next::FromWire::from_wire(wire.vmo_id),
100
101 vmo: ::fidl_next::FromWire::from_wire(wire.vmo),
102
103 rights: ::fidl_next::FromWire::from_wire(wire.rights),
104 }
105 }
106 }
107
108 #[derive(Debug, PartialEq)]
109 #[repr(C)]
110 pub struct SpiImplUnregisterVmoResponse {
111 pub vmo: ::fidl_next::fuchsia::zx::Vmo,
112 }
113
114 unsafe impl<___E> ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>
115 for SpiImplUnregisterVmoResponse
116 where
117 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
118 ___E: ::fidl_next::fuchsia::HandleEncoder,
119 {
120 const COPY_OPTIMIZATION: ::fidl_next::CopyOptimization<
121 Self,
122 crate::wire::SpiImplUnregisterVmoResponse,
123 > = unsafe {
124 ::fidl_next::CopyOptimization::enable_if(
125 true && <::fidl_next::fuchsia::zx::Vmo as ::fidl_next::Encode<
126 ::fidl_next::wire::fuchsia::Vmo,
127 ___E,
128 >>::COPY_OPTIMIZATION
129 .is_enabled(),
130 )
131 };
132
133 #[inline]
134 fn encode(
135 self,
136 encoder_: &mut ___E,
137 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplUnregisterVmoResponse>,
138 _: (),
139 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
140 ::fidl_next::munge! {
141 let crate::wire::SpiImplUnregisterVmoResponse {
142 vmo,
143
144 } = out_;
145 }
146
147 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
148
149 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo.as_mut_ptr()) };
150
151 Ok(())
152 }
153 }
154
155 unsafe impl<___E>
156 ::fidl_next::EncodeOption<
157 ::fidl_next::wire::Box<'static, crate::wire::SpiImplUnregisterVmoResponse>,
158 ___E,
159 > for SpiImplUnregisterVmoResponse
160 where
161 ___E: ::fidl_next::Encoder + ?Sized,
162 SpiImplUnregisterVmoResponse:
163 ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>,
164 {
165 #[inline]
166 fn encode_option(
167 this: ::core::option::Option<Self>,
168 encoder: &mut ___E,
169 out: &mut ::core::mem::MaybeUninit<
170 ::fidl_next::wire::Box<'static, crate::wire::SpiImplUnregisterVmoResponse>,
171 >,
172 _: (),
173 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
174 if let Some(inner) = this {
175 ::fidl_next::EncoderExt::encode_next(encoder, inner)?;
176 ::fidl_next::wire::Box::encode_present(out);
177 } else {
178 ::fidl_next::wire::Box::encode_absent(out);
179 }
180
181 Ok(())
182 }
183 }
184
185 impl ::fidl_next::FromWire<crate::wire::SpiImplUnregisterVmoResponse>
186 for SpiImplUnregisterVmoResponse
187 {
188 const COPY_OPTIMIZATION: ::fidl_next::CopyOptimization<
189 crate::wire::SpiImplUnregisterVmoResponse,
190 Self,
191 > = unsafe {
192 ::fidl_next::CopyOptimization::enable_if(
193 true && <::fidl_next::fuchsia::zx::Vmo as ::fidl_next::FromWire<
194 ::fidl_next::wire::fuchsia::Vmo,
195 >>::COPY_OPTIMIZATION
196 .is_enabled(),
197 )
198 };
199
200 #[inline]
201 fn from_wire(wire: crate::wire::SpiImplUnregisterVmoResponse) -> Self {
202 Self { vmo: ::fidl_next::FromWire::from_wire(wire.vmo) }
203 }
204 }
205}
206
207pub mod wire {
208
209 pub use fidl_next_common_fuchsia_hardware_spiimpl::wire::*;
210
211 #[derive(Debug)]
213 #[repr(C)]
214 pub struct SpiImplRegisterVmoRequest {
215 pub chip_select: ::fidl_next::wire::Uint32,
216
217 pub vmo_id: ::fidl_next::wire::Uint32,
218
219 pub vmo: ::fidl_next_fuchsia_mem::wire::Range,
220
221 pub rights: ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
222 }
223
224 static_assertions::const_assert_eq!(std::mem::size_of::<SpiImplRegisterVmoRequest>(), 40);
225 static_assertions::const_assert_eq!(std::mem::align_of::<SpiImplRegisterVmoRequest>(), 8);
226
227 static_assertions::const_assert_eq!(
228 std::mem::offset_of!(SpiImplRegisterVmoRequest, chip_select),
229 0
230 );
231
232 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplRegisterVmoRequest, vmo_id), 4);
233
234 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplRegisterVmoRequest, vmo), 8);
235
236 static_assertions::const_assert_eq!(
237 std::mem::offset_of!(SpiImplRegisterVmoRequest, rights),
238 32
239 );
240
241 impl ::fidl_next::Constrained for SpiImplRegisterVmoRequest {
242 type Constraint = ();
243
244 fn validate(
245 _: ::fidl_next::Slot<'_, Self>,
246 _: Self::Constraint,
247 ) -> Result<(), ::fidl_next::ValidationError> {
248 Ok(())
249 }
250 }
251
252 unsafe impl ::fidl_next::Wire for SpiImplRegisterVmoRequest {
253 type Narrowed<'de> = SpiImplRegisterVmoRequest;
254
255 #[inline]
256 fn zero_padding(out_: &mut ::core::mem::MaybeUninit<Self>) {
257 ::fidl_next::munge! {
258 let Self {
259 chip_select,
260 vmo_id,
261 vmo,
262 rights,
263
264 } = &mut *out_;
265 }
266
267 ::fidl_next::Wire::zero_padding(chip_select);
268
269 ::fidl_next::Wire::zero_padding(vmo_id);
270
271 ::fidl_next::Wire::zero_padding(vmo);
272
273 ::fidl_next::Wire::zero_padding(rights);
274
275 unsafe {
276 out_.as_mut_ptr().cast::<u8>().add(36).write_bytes(0, 4);
277 }
278 }
279 }
280
281 unsafe impl<___D> ::fidl_next::Decode<___D> for SpiImplRegisterVmoRequest
282 where
283 ___D: ::fidl_next::decoder::InternalHandleDecoder + ?Sized,
284 ___D: ::fidl_next::fuchsia::HandleDecoder,
285 {
286 fn decode(
287 slot_: ::fidl_next::Slot<'_, Self>,
288 decoder_: &mut ___D,
289 _: (),
290 ) -> ::core::result::Result<(), ::fidl_next::DecodeError> {
291 if slot_.as_bytes()[36..40] != [0u8; 4] {
292 return Err(::fidl_next::DecodeError::InvalidPadding);
293 }
294
295 ::fidl_next::munge! {
296 let Self {
297 mut chip_select,
298 mut vmo_id,
299 mut vmo,
300 mut rights,
301
302 } = slot_;
303 }
304
305 let _field = chip_select.as_mut();
306
307 ::fidl_next::Decode::decode(chip_select.as_mut(), decoder_, ())?;
308
309 let _field = vmo_id.as_mut();
310
311 ::fidl_next::Decode::decode(vmo_id.as_mut(), decoder_, ())?;
312
313 let _field = vmo.as_mut();
314
315 ::fidl_next::Decode::decode(vmo.as_mut(), decoder_, ())?;
316
317 let _field = rights.as_mut();
318
319 ::fidl_next::Decode::decode(rights.as_mut(), decoder_, ())?;
320
321 Ok(())
322 }
323 }
324
325 impl ::fidl_next::IntoNatural for SpiImplRegisterVmoRequest {
326 type Natural = crate::natural::SpiImplRegisterVmoRequest;
327 }
328
329 #[derive(Debug)]
331 #[repr(C)]
332 pub struct SpiImplUnregisterVmoResponse {
333 pub vmo: ::fidl_next::wire::fuchsia::Vmo,
334 }
335
336 static_assertions::const_assert_eq!(std::mem::size_of::<SpiImplUnregisterVmoResponse>(), 4);
337 static_assertions::const_assert_eq!(std::mem::align_of::<SpiImplUnregisterVmoResponse>(), 4);
338
339 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplUnregisterVmoResponse, vmo), 0);
340
341 impl ::fidl_next::Constrained for SpiImplUnregisterVmoResponse {
342 type Constraint = ();
343
344 fn validate(
345 _: ::fidl_next::Slot<'_, Self>,
346 _: Self::Constraint,
347 ) -> Result<(), ::fidl_next::ValidationError> {
348 Ok(())
349 }
350 }
351
352 unsafe impl ::fidl_next::Wire for SpiImplUnregisterVmoResponse {
353 type Narrowed<'de> = SpiImplUnregisterVmoResponse;
354
355 #[inline]
356 fn zero_padding(out_: &mut ::core::mem::MaybeUninit<Self>) {
357 ::fidl_next::munge! {
358 let Self {
359 vmo,
360
361 } = &mut *out_;
362 }
363
364 ::fidl_next::Wire::zero_padding(vmo);
365 }
366 }
367
368 unsafe impl<___D> ::fidl_next::Decode<___D> for SpiImplUnregisterVmoResponse
369 where
370 ___D: ::fidl_next::decoder::InternalHandleDecoder + ?Sized,
371 ___D: ::fidl_next::fuchsia::HandleDecoder,
372 {
373 fn decode(
374 slot_: ::fidl_next::Slot<'_, Self>,
375 decoder_: &mut ___D,
376 _: (),
377 ) -> ::core::result::Result<(), ::fidl_next::DecodeError> {
378 ::fidl_next::munge! {
379 let Self {
380 mut vmo,
381
382 } = slot_;
383 }
384
385 let _field = vmo.as_mut();
386
387 ::fidl_next::Decode::decode(vmo.as_mut(), decoder_, ())?;
388
389 Ok(())
390 }
391 }
392
393 impl ::fidl_next::IntoNatural for SpiImplUnregisterVmoResponse {
394 type Natural = crate::natural::SpiImplUnregisterVmoResponse;
395 }
396}
397
398pub mod wire_optional {
399
400 pub use fidl_next_common_fuchsia_hardware_spiimpl::wire_optional::*;
401}
402
403pub mod generic {
404
405 pub use fidl_next_common_fuchsia_hardware_spiimpl::generic::*;
406
407 pub struct SpiImplRegisterVmoRequest<T0, T1, T2, T3> {
409 pub chip_select: T0,
410
411 pub vmo_id: T1,
412
413 pub vmo: T2,
414
415 pub rights: T3,
416 }
417
418 unsafe impl<___E, T0, T1, T2, T3>
419 ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>
420 for SpiImplRegisterVmoRequest<T0, T1, T2, T3>
421 where
422 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
423 ___E: ::fidl_next::fuchsia::HandleEncoder,
424 T0: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
425 T1: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
426 T2: ::fidl_next::Encode<::fidl_next_fuchsia_mem::wire::Range, ___E>,
427 T3: ::fidl_next::Encode<
428 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
429 ___E,
430 >,
431 {
432 #[inline]
433 fn encode(
434 self,
435 encoder_: &mut ___E,
436 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplRegisterVmoRequest>,
437 _: (),
438 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
439 ::fidl_next::munge! {
440 let crate::wire::SpiImplRegisterVmoRequest {
441 chip_select,
442 vmo_id,
443 vmo,
444 rights,
445
446 } = out_;
447 }
448
449 ::fidl_next::Encode::encode(self.chip_select, encoder_, chip_select, ())?;
450
451 ::fidl_next::Encode::encode(self.vmo_id, encoder_, vmo_id, ())?;
452
453 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
454
455 ::fidl_next::Encode::encode(self.rights, encoder_, rights, ())?;
456
457 Ok(())
458 }
459 }
460
461 pub struct SpiImplUnregisterVmoResponse<T0> {
463 pub vmo: T0,
464 }
465
466 unsafe impl<___E, T0> ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>
467 for SpiImplUnregisterVmoResponse<T0>
468 where
469 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
470 ___E: ::fidl_next::fuchsia::HandleEncoder,
471 T0: ::fidl_next::Encode<::fidl_next::wire::fuchsia::Vmo, ___E>,
472 {
473 #[inline]
474 fn encode(
475 self,
476 encoder_: &mut ___E,
477 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplUnregisterVmoResponse>,
478 _: (),
479 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
480 ::fidl_next::munge! {
481 let crate::wire::SpiImplUnregisterVmoResponse {
482 vmo,
483
484 } = out_;
485 }
486
487 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
488
489 Ok(())
490 }
491 }
492}
493
494pub use self::natural::*;
495
496#[derive(Debug)]
498pub struct Service;
499
500impl ::fidl_next::DiscoverableService for Service {
501 const SERVICE_NAME: &'static str = "fuchsia.hardware.spiimpl.Service";
502 const MEMBER_NAMES: &'static [&'static str] = &["device"];
503}
504
505impl ::fidl_next::HasServiceRequest<::fdf_fidl::DriverChannel> for Service {}
506
507impl<___C> ::fidl_next::Service<___C> for Service
508where
509 ___C: ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>,
510{
511 type Connector = ServiceConnector<___C>;
512}
513
514#[repr(transparent)]
516pub struct ServiceConnector<___C> {
517 #[allow(dead_code)]
518 connector: ___C,
519}
520
521impl<___C> ServiceConnector<___C>
522where
523 ___C: ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>,
524{
525 pub fn device(
527 &self,
528 server_end: ::fidl_next::ServerEnd<crate::SpiImpl, ::fdf_fidl::DriverChannel>,
529 ) -> ::core::result::Result<
530 (),
531 <___C as ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>>::Error,
532 > {
533 ::fidl_next::protocol::ServiceConnector::<::fdf_fidl::DriverChannel>::connect_to_member(
534 &self.connector,
535 "device",
536 server_end.into_untyped(),
537 )
538 }
539}
540
541pub trait ServiceHandler {
543 fn device(&self, server_end: ::fidl_next::ServerEnd<crate::SpiImpl, ::fdf_fidl::DriverChannel>);
545}
546
547impl<___H, ___T> ::fidl_next::DispatchServiceHandler<___H, ___T> for Service
548where
549 ___H: ServiceHandler,
550 ::fdf_fidl::DriverChannel: ::fidl_next::InstanceFromServiceTransport<___T>,
551{
552 fn on_connection(handler: &___H, member: &str, server_end: ___T) {
553 use ::fidl_next::InstanceFromServiceTransport;
554 match member {
555 "device" => handler.device(::fidl_next::ServerEnd::from_untyped(
556 ::fdf_fidl::DriverChannel::from_service_transport(server_end),
557 )),
558
559 _ => unreachable!(),
560 }
561 }
562}
563
564#[doc = " Low-level protocol for spi drivers.\n"]
566#[derive(PartialEq, Debug)]
567pub struct SpiImpl;
568
569impl ::fidl_next::Discoverable for SpiImpl {
570 const PROTOCOL_NAME: &'static str = "fuchsia.hardware.spiimpl.SpiImpl";
571}
572
573#[cfg(feature = "driver")]
574impl ::fidl_next::HasTransport for SpiImpl {
575 type Transport = ::fdf_fidl::DriverChannel;
576}
577
578pub mod spi_impl {
579 pub mod prelude {
580 pub use crate::{
581 SpiImpl, SpiImplClientHandler, SpiImplLocalClientHandler, SpiImplLocalServerHandler,
582 SpiImplServerHandler, spi_impl,
583 };
584
585 pub use crate::natural::SpiImplExchangeVectorRequest;
586
587 pub use crate::natural::SpiImplExchangeVmoRequest;
588
589 pub use crate::natural::SpiImplGetChipSelectCountResponse;
590
591 pub use crate::natural::SpiImplLockBusRequest;
592
593 pub use crate::natural::SpiImplReceiveVectorRequest;
594
595 pub use crate::natural::SpiImplReceiveVmoRequest;
596
597 pub use crate::natural::SpiImplRegisterVmoRequest;
598
599 pub use crate::natural::SpiImplReleaseRegisteredVmosRequest;
600
601 pub use crate::natural::SpiImplTransmitVectorRequest;
602
603 pub use crate::natural::SpiImplTransmitVmoRequest;
604
605 pub use crate::natural::SpiImplUnlockBusRequest;
606
607 pub use crate::natural::SpiImplUnregisterVmoRequest;
608
609 pub use crate::natural::SpiImplExchangeVectorResponse;
610
611 pub use crate::natural::SpiImplExchangeVmoResponse;
612
613 pub use crate::natural::SpiImplLockBusResponse;
614
615 pub use crate::natural::SpiImplReceiveVectorResponse;
616
617 pub use crate::natural::SpiImplReceiveVmoResponse;
618
619 pub use crate::natural::SpiImplRegisterVmoResponse;
620
621 pub use crate::natural::SpiImplTransmitVectorResponse;
622
623 pub use crate::natural::SpiImplTransmitVmoResponse;
624
625 pub use crate::natural::SpiImplUnlockBusResponse;
626
627 pub use crate::natural::SpiImplUnregisterVmoResponse;
628 }
629
630 pub struct GetChipSelectCount;
631
632 impl ::fidl_next::Method for GetChipSelectCount {
633 const ORDINAL: u64 = 4261972386852856527;
634 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
635 ::fidl_next::protocol::Flexibility::Strict;
636
637 type Protocol = crate::SpiImpl;
638
639 type Request = ::fidl_next::wire::EmptyMessageBody;
640 }
641
642 impl ::fidl_next::TwoWayMethod for GetChipSelectCount {
643 type Response = crate::wire::SpiImplGetChipSelectCountResponse;
644 }
645
646 impl<___R> ::fidl_next::Respond<___R> for GetChipSelectCount {
647 type Output = crate::generic::SpiImplGetChipSelectCountResponse<___R>;
648
649 fn respond(response: ___R) -> Self::Output {
650 crate::generic::SpiImplGetChipSelectCountResponse { count: response }
651 }
652 }
653
654 pub struct TransmitVector;
655
656 impl ::fidl_next::Method for TransmitVector {
657 const ORDINAL: u64 = 7287789131276374998;
658 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
659 ::fidl_next::protocol::Flexibility::Strict;
660
661 type Protocol = crate::SpiImpl;
662
663 type Request = crate::wire::SpiImplTransmitVectorRequest<'static>;
664 }
665
666 impl ::fidl_next::TwoWayMethod for TransmitVector {
667 type Response = ::fidl_next::wire::Result<
668 'static,
669 crate::wire::SpiImplTransmitVectorResponse,
670 ::fidl_next::wire::Int32,
671 >;
672 }
673
674 impl<___R> ::fidl_next::Respond<___R> for TransmitVector {
675 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
676
677 fn respond(response: ___R) -> Self::Output {
678 ::core::result::Result::Ok(response)
679 }
680 }
681
682 impl<___R> ::fidl_next::RespondErr<___R> for TransmitVector {
683 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
684
685 fn respond_err(response: ___R) -> Self::Output {
686 ::core::result::Result::Err(response)
687 }
688 }
689
690 pub struct ReceiveVector;
691
692 impl ::fidl_next::Method for ReceiveVector {
693 const ORDINAL: u64 = 4813495552606122700;
694 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
695 ::fidl_next::protocol::Flexibility::Strict;
696
697 type Protocol = crate::SpiImpl;
698
699 type Request = crate::wire::SpiImplReceiveVectorRequest;
700 }
701
702 impl ::fidl_next::TwoWayMethod for ReceiveVector {
703 type Response = ::fidl_next::wire::Result<
704 'static,
705 crate::wire::SpiImplReceiveVectorResponse<'static>,
706 ::fidl_next::wire::Int32,
707 >;
708 }
709
710 impl<___R> ::fidl_next::Respond<___R> for ReceiveVector {
711 type Output = ::core::result::Result<
712 crate::generic::SpiImplReceiveVectorResponse<___R>,
713 ::fidl_next::util::Never,
714 >;
715
716 fn respond(response: ___R) -> Self::Output {
717 ::core::result::Result::Ok(crate::generic::SpiImplReceiveVectorResponse {
718 data: response,
719 })
720 }
721 }
722
723 impl<___R> ::fidl_next::RespondErr<___R> for ReceiveVector {
724 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
725
726 fn respond_err(response: ___R) -> Self::Output {
727 ::core::result::Result::Err(response)
728 }
729 }
730
731 pub struct ExchangeVector;
732
733 impl ::fidl_next::Method for ExchangeVector {
734 const ORDINAL: u64 = 3844617764012354164;
735 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
736 ::fidl_next::protocol::Flexibility::Strict;
737
738 type Protocol = crate::SpiImpl;
739
740 type Request = crate::wire::SpiImplExchangeVectorRequest<'static>;
741 }
742
743 impl ::fidl_next::TwoWayMethod for ExchangeVector {
744 type Response = ::fidl_next::wire::Result<
745 'static,
746 crate::wire::SpiImplExchangeVectorResponse<'static>,
747 ::fidl_next::wire::Int32,
748 >;
749 }
750
751 impl<___R> ::fidl_next::Respond<___R> for ExchangeVector {
752 type Output = ::core::result::Result<
753 crate::generic::SpiImplExchangeVectorResponse<___R>,
754 ::fidl_next::util::Never,
755 >;
756
757 fn respond(response: ___R) -> Self::Output {
758 ::core::result::Result::Ok(crate::generic::SpiImplExchangeVectorResponse {
759 rxdata: response,
760 })
761 }
762 }
763
764 impl<___R> ::fidl_next::RespondErr<___R> for ExchangeVector {
765 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
766
767 fn respond_err(response: ___R) -> Self::Output {
768 ::core::result::Result::Err(response)
769 }
770 }
771
772 pub struct LockBus;
773
774 impl ::fidl_next::Method for LockBus {
775 const ORDINAL: u64 = 9187537331803160557;
776 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
777 ::fidl_next::protocol::Flexibility::Strict;
778
779 type Protocol = crate::SpiImpl;
780
781 type Request = crate::wire::SpiImplLockBusRequest;
782 }
783
784 impl ::fidl_next::TwoWayMethod for LockBus {
785 type Response = ::fidl_next::wire::Result<
786 'static,
787 crate::wire::SpiImplLockBusResponse,
788 ::fidl_next::wire::Int32,
789 >;
790 }
791
792 impl<___R> ::fidl_next::Respond<___R> for LockBus {
793 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
794
795 fn respond(response: ___R) -> Self::Output {
796 ::core::result::Result::Ok(response)
797 }
798 }
799
800 impl<___R> ::fidl_next::RespondErr<___R> for LockBus {
801 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
802
803 fn respond_err(response: ___R) -> Self::Output {
804 ::core::result::Result::Err(response)
805 }
806 }
807
808 pub struct UnlockBus;
809
810 impl ::fidl_next::Method for UnlockBus {
811 const ORDINAL: u64 = 3150764477565251378;
812 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
813 ::fidl_next::protocol::Flexibility::Strict;
814
815 type Protocol = crate::SpiImpl;
816
817 type Request = crate::wire::SpiImplUnlockBusRequest;
818 }
819
820 impl ::fidl_next::TwoWayMethod for UnlockBus {
821 type Response = ::fidl_next::wire::Result<
822 'static,
823 crate::wire::SpiImplUnlockBusResponse,
824 ::fidl_next::wire::Int32,
825 >;
826 }
827
828 impl<___R> ::fidl_next::Respond<___R> for UnlockBus {
829 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
830
831 fn respond(response: ___R) -> Self::Output {
832 ::core::result::Result::Ok(response)
833 }
834 }
835
836 impl<___R> ::fidl_next::RespondErr<___R> for UnlockBus {
837 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
838
839 fn respond_err(response: ___R) -> Self::Output {
840 ::core::result::Result::Err(response)
841 }
842 }
843
844 pub struct RegisterVmo;
845
846 impl ::fidl_next::Method for RegisterVmo {
847 const ORDINAL: u64 = 2270783649342134233;
848 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
849 ::fidl_next::protocol::Flexibility::Strict;
850
851 type Protocol = crate::SpiImpl;
852
853 type Request = crate::wire::SpiImplRegisterVmoRequest;
854 }
855
856 impl ::fidl_next::TwoWayMethod for RegisterVmo {
857 type Response = ::fidl_next::wire::Result<
858 'static,
859 crate::wire::SpiImplRegisterVmoResponse,
860 ::fidl_next::wire::Int32,
861 >;
862 }
863
864 impl<___R> ::fidl_next::Respond<___R> for RegisterVmo {
865 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
866
867 fn respond(response: ___R) -> Self::Output {
868 ::core::result::Result::Ok(response)
869 }
870 }
871
872 impl<___R> ::fidl_next::RespondErr<___R> for RegisterVmo {
873 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
874
875 fn respond_err(response: ___R) -> Self::Output {
876 ::core::result::Result::Err(response)
877 }
878 }
879
880 pub struct UnregisterVmo;
881
882 impl ::fidl_next::Method for UnregisterVmo {
883 const ORDINAL: u64 = 8778583385931240091;
884 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
885 ::fidl_next::protocol::Flexibility::Strict;
886
887 type Protocol = crate::SpiImpl;
888
889 type Request = crate::wire::SpiImplUnregisterVmoRequest;
890 }
891
892 impl ::fidl_next::TwoWayMethod for UnregisterVmo {
893 type Response = ::fidl_next::wire::Result<
894 'static,
895 crate::wire::SpiImplUnregisterVmoResponse,
896 ::fidl_next::wire::Int32,
897 >;
898 }
899
900 impl<___R> ::fidl_next::Respond<___R> for UnregisterVmo {
901 type Output = ::core::result::Result<
902 crate::generic::SpiImplUnregisterVmoResponse<___R>,
903 ::fidl_next::util::Never,
904 >;
905
906 fn respond(response: ___R) -> Self::Output {
907 ::core::result::Result::Ok(crate::generic::SpiImplUnregisterVmoResponse {
908 vmo: response,
909 })
910 }
911 }
912
913 impl<___R> ::fidl_next::RespondErr<___R> for UnregisterVmo {
914 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
915
916 fn respond_err(response: ___R) -> Self::Output {
917 ::core::result::Result::Err(response)
918 }
919 }
920
921 pub struct ReleaseRegisteredVmos;
922
923 impl ::fidl_next::Method for ReleaseRegisteredVmos {
924 const ORDINAL: u64 = 5302547493468731494;
925 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
926 ::fidl_next::protocol::Flexibility::Strict;
927
928 type Protocol = crate::SpiImpl;
929
930 type Request = crate::wire::SpiImplReleaseRegisteredVmosRequest;
931 }
932
933 pub struct TransmitVmo;
934
935 impl ::fidl_next::Method for TransmitVmo {
936 const ORDINAL: u64 = 1490935665662854691;
937 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
938 ::fidl_next::protocol::Flexibility::Strict;
939
940 type Protocol = crate::SpiImpl;
941
942 type Request = crate::wire::SpiImplTransmitVmoRequest;
943 }
944
945 impl ::fidl_next::TwoWayMethod for TransmitVmo {
946 type Response = ::fidl_next::wire::Result<
947 'static,
948 crate::wire::SpiImplTransmitVmoResponse,
949 ::fidl_next::wire::Int32,
950 >;
951 }
952
953 impl<___R> ::fidl_next::Respond<___R> for TransmitVmo {
954 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
955
956 fn respond(response: ___R) -> Self::Output {
957 ::core::result::Result::Ok(response)
958 }
959 }
960
961 impl<___R> ::fidl_next::RespondErr<___R> for TransmitVmo {
962 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
963
964 fn respond_err(response: ___R) -> Self::Output {
965 ::core::result::Result::Err(response)
966 }
967 }
968
969 pub struct ReceiveVmo;
970
971 impl ::fidl_next::Method for ReceiveVmo {
972 const ORDINAL: u64 = 7091744647492940488;
973 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
974 ::fidl_next::protocol::Flexibility::Strict;
975
976 type Protocol = crate::SpiImpl;
977
978 type Request = crate::wire::SpiImplReceiveVmoRequest;
979 }
980
981 impl ::fidl_next::TwoWayMethod for ReceiveVmo {
982 type Response = ::fidl_next::wire::Result<
983 'static,
984 crate::wire::SpiImplReceiveVmoResponse,
985 ::fidl_next::wire::Int32,
986 >;
987 }
988
989 impl<___R> ::fidl_next::Respond<___R> for ReceiveVmo {
990 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
991
992 fn respond(response: ___R) -> Self::Output {
993 ::core::result::Result::Ok(response)
994 }
995 }
996
997 impl<___R> ::fidl_next::RespondErr<___R> for ReceiveVmo {
998 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
999
1000 fn respond_err(response: ___R) -> Self::Output {
1001 ::core::result::Result::Err(response)
1002 }
1003 }
1004
1005 pub struct ExchangeVmo;
1006
1007 impl ::fidl_next::Method for ExchangeVmo {
1008 const ORDINAL: u64 = 3592177641282126076;
1009 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
1010 ::fidl_next::protocol::Flexibility::Strict;
1011
1012 type Protocol = crate::SpiImpl;
1013
1014 type Request = crate::wire::SpiImplExchangeVmoRequest;
1015 }
1016
1017 impl ::fidl_next::TwoWayMethod for ExchangeVmo {
1018 type Response = ::fidl_next::wire::Result<
1019 'static,
1020 crate::wire::SpiImplExchangeVmoResponse,
1021 ::fidl_next::wire::Int32,
1022 >;
1023 }
1024
1025 impl<___R> ::fidl_next::Respond<___R> for ExchangeVmo {
1026 type Output = ::core::result::Result<___R, ::fidl_next::util::Never>;
1027
1028 fn respond(response: ___R) -> Self::Output {
1029 ::core::result::Result::Ok(response)
1030 }
1031 }
1032
1033 impl<___R> ::fidl_next::RespondErr<___R> for ExchangeVmo {
1034 type Output = ::core::result::Result<::fidl_next::util::Never, ___R>;
1035
1036 fn respond_err(response: ___R) -> Self::Output {
1037 ::core::result::Result::Err(response)
1038 }
1039 }
1040
1041 mod ___detail {
1042 unsafe impl<___T> ::fidl_next::HasConnectionHandles<___T> for crate::SpiImpl
1043 where
1044 ___T: ::fidl_next::Transport,
1045 {
1046 type Client = SpiImplClient<___T>;
1047 type Server = SpiImplServer<___T>;
1048 }
1049
1050 #[repr(transparent)]
1052 pub struct SpiImplClient<___T: ::fidl_next::Transport> {
1053 #[allow(dead_code)]
1054 client: ::fidl_next::protocol::Client<___T>,
1055 }
1056
1057 impl<___T> SpiImplClient<___T>
1058 where
1059 ___T: ::fidl_next::Transport,
1060 {
1061 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
1062 pub fn get_chip_select_count(
1063 &self,
1064 ) -> ::fidl_next::TwoWayFuture<'_, super::GetChipSelectCount, ___T> {
1065 ::fidl_next::TwoWayFuture::from_untyped(
1066 self.client.send_two_way::<::fidl_next::wire::EmptyMessageBody>(
1067 4261972386852856527,
1068 <super::GetChipSelectCount as ::fidl_next::Method>::FLEXIBILITY,
1069 (),
1070 ),
1071 )
1072 }
1073
1074 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1075 pub fn transmit_vector(
1076 &self,
1077
1078 chip_select: impl ::fidl_next::Encode<
1079 ::fidl_next::wire::Uint32,
1080 <___T as ::fidl_next::Transport>::SendBuffer,
1081 >,
1082
1083 data: impl ::fidl_next::Encode<
1084 ::fidl_next::wire::Vector<'static, u8>,
1085 <___T as ::fidl_next::Transport>::SendBuffer,
1086 >,
1087 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVector, ___T>
1088 where
1089 <___T as ::fidl_next::Transport>::SendBuffer:
1090 ::fidl_next::encoder::InternalHandleEncoder,
1091 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::Encoder,
1092 {
1093 self.transmit_vector_with(crate::generic::SpiImplTransmitVectorRequest {
1094 chip_select,
1095
1096 data,
1097 })
1098 }
1099
1100 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1101 pub fn transmit_vector_with<___R>(
1102 &self,
1103 request: ___R,
1104 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVector, ___T>
1105 where
1106 ___R: ::fidl_next::Encode<
1107 crate::wire::SpiImplTransmitVectorRequest<'static>,
1108 <___T as ::fidl_next::Transport>::SendBuffer,
1109 >,
1110 {
1111 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1112 7287789131276374998,
1113 <super::TransmitVector as ::fidl_next::Method>::FLEXIBILITY,
1114 request,
1115 ))
1116 }
1117
1118 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1119 pub fn receive_vector(
1120 &self,
1121
1122 chip_select: impl ::fidl_next::Encode<
1123 ::fidl_next::wire::Uint32,
1124 <___T as ::fidl_next::Transport>::SendBuffer,
1125 >,
1126
1127 size: impl ::fidl_next::Encode<
1128 ::fidl_next::wire::Uint32,
1129 <___T as ::fidl_next::Transport>::SendBuffer,
1130 >,
1131 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVector, ___T>
1132 where
1133 <___T as ::fidl_next::Transport>::SendBuffer:
1134 ::fidl_next::encoder::InternalHandleEncoder,
1135 {
1136 self.receive_vector_with(crate::generic::SpiImplReceiveVectorRequest {
1137 chip_select,
1138
1139 size,
1140 })
1141 }
1142
1143 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1144 pub fn receive_vector_with<___R>(
1145 &self,
1146 request: ___R,
1147 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVector, ___T>
1148 where
1149 ___R: ::fidl_next::Encode<
1150 crate::wire::SpiImplReceiveVectorRequest,
1151 <___T as ::fidl_next::Transport>::SendBuffer,
1152 >,
1153 {
1154 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1155 4813495552606122700,
1156 <super::ReceiveVector as ::fidl_next::Method>::FLEXIBILITY,
1157 request,
1158 ))
1159 }
1160
1161 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1162 pub fn exchange_vector(
1163 &self,
1164
1165 chip_select: impl ::fidl_next::Encode<
1166 ::fidl_next::wire::Uint32,
1167 <___T as ::fidl_next::Transport>::SendBuffer,
1168 >,
1169
1170 txdata: impl ::fidl_next::Encode<
1171 ::fidl_next::wire::Vector<'static, u8>,
1172 <___T as ::fidl_next::Transport>::SendBuffer,
1173 >,
1174 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVector, ___T>
1175 where
1176 <___T as ::fidl_next::Transport>::SendBuffer:
1177 ::fidl_next::encoder::InternalHandleEncoder,
1178 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::Encoder,
1179 {
1180 self.exchange_vector_with(crate::generic::SpiImplExchangeVectorRequest {
1181 chip_select,
1182
1183 txdata,
1184 })
1185 }
1186
1187 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1188 pub fn exchange_vector_with<___R>(
1189 &self,
1190 request: ___R,
1191 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVector, ___T>
1192 where
1193 ___R: ::fidl_next::Encode<
1194 crate::wire::SpiImplExchangeVectorRequest<'static>,
1195 <___T as ::fidl_next::Transport>::SendBuffer,
1196 >,
1197 {
1198 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1199 3844617764012354164,
1200 <super::ExchangeVector as ::fidl_next::Method>::FLEXIBILITY,
1201 request,
1202 ))
1203 }
1204
1205 #[doc = " Lock the bus.\n"]
1206 pub fn lock_bus(
1207 &self,
1208
1209 chip_select: impl ::fidl_next::Encode<
1210 ::fidl_next::wire::Uint32,
1211 <___T as ::fidl_next::Transport>::SendBuffer,
1212 >,
1213 ) -> ::fidl_next::TwoWayFuture<'_, super::LockBus, ___T>
1214 where
1215 <___T as ::fidl_next::Transport>::SendBuffer:
1216 ::fidl_next::encoder::InternalHandleEncoder,
1217 {
1218 self.lock_bus_with(crate::generic::SpiImplLockBusRequest { chip_select })
1219 }
1220
1221 #[doc = " Lock the bus.\n"]
1222 pub fn lock_bus_with<___R>(
1223 &self,
1224 request: ___R,
1225 ) -> ::fidl_next::TwoWayFuture<'_, super::LockBus, ___T>
1226 where
1227 ___R: ::fidl_next::Encode<
1228 crate::wire::SpiImplLockBusRequest,
1229 <___T as ::fidl_next::Transport>::SendBuffer,
1230 >,
1231 {
1232 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1233 9187537331803160557,
1234 <super::LockBus as ::fidl_next::Method>::FLEXIBILITY,
1235 request,
1236 ))
1237 }
1238
1239 #[doc = " Unlock the bus.\n"]
1240 pub fn unlock_bus(
1241 &self,
1242
1243 chip_select: impl ::fidl_next::Encode<
1244 ::fidl_next::wire::Uint32,
1245 <___T as ::fidl_next::Transport>::SendBuffer,
1246 >,
1247 ) -> ::fidl_next::TwoWayFuture<'_, super::UnlockBus, ___T>
1248 where
1249 <___T as ::fidl_next::Transport>::SendBuffer:
1250 ::fidl_next::encoder::InternalHandleEncoder,
1251 {
1252 self.unlock_bus_with(crate::generic::SpiImplUnlockBusRequest { chip_select })
1253 }
1254
1255 #[doc = " Unlock the bus.\n"]
1256 pub fn unlock_bus_with<___R>(
1257 &self,
1258 request: ___R,
1259 ) -> ::fidl_next::TwoWayFuture<'_, super::UnlockBus, ___T>
1260 where
1261 ___R: ::fidl_next::Encode<
1262 crate::wire::SpiImplUnlockBusRequest,
1263 <___T as ::fidl_next::Transport>::SendBuffer,
1264 >,
1265 {
1266 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1267 3150764477565251378,
1268 <super::UnlockBus as ::fidl_next::Method>::FLEXIBILITY,
1269 request,
1270 ))
1271 }
1272
1273 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1274 pub fn register_vmo(
1275 &self,
1276
1277 chip_select: impl ::fidl_next::Encode<
1278 ::fidl_next::wire::Uint32,
1279 <___T as ::fidl_next::Transport>::SendBuffer,
1280 >,
1281
1282 vmo_id: impl ::fidl_next::Encode<
1283 ::fidl_next::wire::Uint32,
1284 <___T as ::fidl_next::Transport>::SendBuffer,
1285 >,
1286
1287 vmo: impl ::fidl_next::Encode<
1288 ::fidl_next_fuchsia_mem::wire::Range,
1289 <___T as ::fidl_next::Transport>::SendBuffer,
1290 >,
1291
1292 rights: impl ::fidl_next::Encode<
1293 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
1294 <___T as ::fidl_next::Transport>::SendBuffer,
1295 >,
1296 ) -> ::fidl_next::TwoWayFuture<'_, super::RegisterVmo, ___T>
1297 where
1298 <___T as ::fidl_next::Transport>::SendBuffer:
1299 ::fidl_next::encoder::InternalHandleEncoder,
1300 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::fuchsia::HandleEncoder,
1301 {
1302 self.register_vmo_with(crate::generic::SpiImplRegisterVmoRequest {
1303 chip_select,
1304
1305 vmo_id,
1306
1307 vmo,
1308
1309 rights,
1310 })
1311 }
1312
1313 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1314 pub fn register_vmo_with<___R>(
1315 &self,
1316 request: ___R,
1317 ) -> ::fidl_next::TwoWayFuture<'_, super::RegisterVmo, ___T>
1318 where
1319 ___R: ::fidl_next::Encode<
1320 crate::wire::SpiImplRegisterVmoRequest,
1321 <___T as ::fidl_next::Transport>::SendBuffer,
1322 >,
1323 {
1324 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1325 2270783649342134233,
1326 <super::RegisterVmo as ::fidl_next::Method>::FLEXIBILITY,
1327 request,
1328 ))
1329 }
1330
1331 pub fn unregister_vmo(
1332 &self,
1333
1334 chip_select: impl ::fidl_next::Encode<
1335 ::fidl_next::wire::Uint32,
1336 <___T as ::fidl_next::Transport>::SendBuffer,
1337 >,
1338
1339 vmo_id: impl ::fidl_next::Encode<
1340 ::fidl_next::wire::Uint32,
1341 <___T as ::fidl_next::Transport>::SendBuffer,
1342 >,
1343 ) -> ::fidl_next::TwoWayFuture<'_, super::UnregisterVmo, ___T>
1344 where
1345 <___T as ::fidl_next::Transport>::SendBuffer:
1346 ::fidl_next::encoder::InternalHandleEncoder,
1347 {
1348 self.unregister_vmo_with(crate::generic::SpiImplUnregisterVmoRequest {
1349 chip_select,
1350
1351 vmo_id,
1352 })
1353 }
1354
1355 pub fn unregister_vmo_with<___R>(
1356 &self,
1357 request: ___R,
1358 ) -> ::fidl_next::TwoWayFuture<'_, super::UnregisterVmo, ___T>
1359 where
1360 ___R: ::fidl_next::Encode<
1361 crate::wire::SpiImplUnregisterVmoRequest,
1362 <___T as ::fidl_next::Transport>::SendBuffer,
1363 >,
1364 {
1365 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1366 8778583385931240091,
1367 <super::UnregisterVmo as ::fidl_next::Method>::FLEXIBILITY,
1368 request,
1369 ))
1370 }
1371
1372 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1373 pub fn release_registered_vmos(
1374 &self,
1375
1376 chip_select: impl ::fidl_next::Encode<
1377 ::fidl_next::wire::Uint32,
1378 <___T as ::fidl_next::Transport>::SendBuffer,
1379 >,
1380 ) -> ::fidl_next::SendFuture<'_, ___T>
1381 where
1382 <___T as ::fidl_next::Transport>::SendBuffer:
1383 ::fidl_next::encoder::InternalHandleEncoder,
1384 {
1385 self.release_registered_vmos_with(
1386 crate::generic::SpiImplReleaseRegisteredVmosRequest { chip_select },
1387 )
1388 }
1389
1390 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1391 pub fn release_registered_vmos_with<___R>(
1392 &self,
1393 request: ___R,
1394 ) -> ::fidl_next::SendFuture<'_, ___T>
1395 where
1396 ___R: ::fidl_next::Encode<
1397 crate::wire::SpiImplReleaseRegisteredVmosRequest,
1398 <___T as ::fidl_next::Transport>::SendBuffer,
1399 >,
1400 {
1401 ::fidl_next::SendFuture::from_untyped(self.client.send_one_way(
1402 5302547493468731494,
1403 <super::ReleaseRegisteredVmos as ::fidl_next::Method>::FLEXIBILITY,
1404 request,
1405 ))
1406 }
1407
1408 pub fn transmit_vmo(
1409 &self,
1410
1411 chip_select: impl ::fidl_next::Encode<
1412 ::fidl_next::wire::Uint32,
1413 <___T as ::fidl_next::Transport>::SendBuffer,
1414 >,
1415
1416 buffer: impl ::fidl_next::Encode<
1417 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1418 <___T as ::fidl_next::Transport>::SendBuffer,
1419 >,
1420 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVmo, ___T>
1421 where
1422 <___T as ::fidl_next::Transport>::SendBuffer:
1423 ::fidl_next::encoder::InternalHandleEncoder,
1424 {
1425 self.transmit_vmo_with(crate::generic::SpiImplTransmitVmoRequest {
1426 chip_select,
1427
1428 buffer,
1429 })
1430 }
1431
1432 pub fn transmit_vmo_with<___R>(
1433 &self,
1434 request: ___R,
1435 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVmo, ___T>
1436 where
1437 ___R: ::fidl_next::Encode<
1438 crate::wire::SpiImplTransmitVmoRequest,
1439 <___T as ::fidl_next::Transport>::SendBuffer,
1440 >,
1441 {
1442 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1443 1490935665662854691,
1444 <super::TransmitVmo as ::fidl_next::Method>::FLEXIBILITY,
1445 request,
1446 ))
1447 }
1448
1449 pub fn receive_vmo(
1450 &self,
1451
1452 chip_select: impl ::fidl_next::Encode<
1453 ::fidl_next::wire::Uint32,
1454 <___T as ::fidl_next::Transport>::SendBuffer,
1455 >,
1456
1457 buffer: impl ::fidl_next::Encode<
1458 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1459 <___T as ::fidl_next::Transport>::SendBuffer,
1460 >,
1461 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVmo, ___T>
1462 where
1463 <___T as ::fidl_next::Transport>::SendBuffer:
1464 ::fidl_next::encoder::InternalHandleEncoder,
1465 {
1466 self.receive_vmo_with(crate::generic::SpiImplReceiveVmoRequest {
1467 chip_select,
1468
1469 buffer,
1470 })
1471 }
1472
1473 pub fn receive_vmo_with<___R>(
1474 &self,
1475 request: ___R,
1476 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVmo, ___T>
1477 where
1478 ___R: ::fidl_next::Encode<
1479 crate::wire::SpiImplReceiveVmoRequest,
1480 <___T as ::fidl_next::Transport>::SendBuffer,
1481 >,
1482 {
1483 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1484 7091744647492940488,
1485 <super::ReceiveVmo as ::fidl_next::Method>::FLEXIBILITY,
1486 request,
1487 ))
1488 }
1489
1490 pub fn exchange_vmo(
1491 &self,
1492
1493 chip_select: impl ::fidl_next::Encode<
1494 ::fidl_next::wire::Uint32,
1495 <___T as ::fidl_next::Transport>::SendBuffer,
1496 >,
1497
1498 tx_buffer: impl ::fidl_next::Encode<
1499 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1500 <___T as ::fidl_next::Transport>::SendBuffer,
1501 >,
1502
1503 rx_buffer: impl ::fidl_next::Encode<
1504 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1505 <___T as ::fidl_next::Transport>::SendBuffer,
1506 >,
1507 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVmo, ___T>
1508 where
1509 <___T as ::fidl_next::Transport>::SendBuffer:
1510 ::fidl_next::encoder::InternalHandleEncoder,
1511 {
1512 self.exchange_vmo_with(crate::generic::SpiImplExchangeVmoRequest {
1513 chip_select,
1514
1515 tx_buffer,
1516
1517 rx_buffer,
1518 })
1519 }
1520
1521 pub fn exchange_vmo_with<___R>(
1522 &self,
1523 request: ___R,
1524 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVmo, ___T>
1525 where
1526 ___R: ::fidl_next::Encode<
1527 crate::wire::SpiImplExchangeVmoRequest,
1528 <___T as ::fidl_next::Transport>::SendBuffer,
1529 >,
1530 {
1531 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1532 3592177641282126076,
1533 <super::ExchangeVmo as ::fidl_next::Method>::FLEXIBILITY,
1534 request,
1535 ))
1536 }
1537 }
1538
1539 #[repr(transparent)]
1541 pub struct SpiImplServer<___T: ::fidl_next::Transport> {
1542 server: ::fidl_next::protocol::Server<___T>,
1543 }
1544
1545 impl<___T> SpiImplServer<___T> where ___T: ::fidl_next::Transport {}
1546 }
1547}
1548
1549#[diagnostic::on_unimplemented(
1550 note = "If {Self} implements the non-local SpiImplClientHandler trait, use `spawn_as_local` or the `Local` adapter type"
1551)]
1552
1553pub trait SpiImplLocalClientHandler<
1557 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1558 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1559>
1560{
1561}
1562
1563impl<___H, ___T> ::fidl_next::DispatchLocalClientMessage<___H, ___T> for SpiImpl
1564where
1565 ___H: SpiImplLocalClientHandler<___T>,
1566 ___T: ::fidl_next::Transport,
1567{
1568 async fn on_event(
1569 handler: &mut ___H,
1570 ordinal: u64,
1571 flexibility: ::fidl_next::protocol::Flexibility,
1572 body: ::fidl_next::Body<___T>,
1573 ) -> ::core::result::Result<(), ::fidl_next::ProtocolError<___T::Error>> {
1574 match ordinal {
1575 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1576 }
1577 }
1578}
1579
1580#[diagnostic::on_unimplemented(
1581 note = "If {Self} implements the non-local SpiImplServerHandler trait, use `spawn_as_local` or the `Local` adapter type"
1582)]
1583
1584pub trait SpiImplLocalServerHandler<
1588 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1589 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1590>
1591{
1592 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
1593 fn get_chip_select_count(
1594 &mut self,
1595
1596 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
1597 ) -> impl ::core::future::Future<Output = ()>;
1598
1599 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1600 fn transmit_vector(
1601 &mut self,
1602
1603 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
1604
1605 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
1606 ) -> impl ::core::future::Future<Output = ()>;
1607
1608 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1609 fn receive_vector(
1610 &mut self,
1611
1612 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
1613
1614 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
1615 ) -> impl ::core::future::Future<Output = ()>;
1616
1617 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1618 fn exchange_vector(
1619 &mut self,
1620
1621 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
1622
1623 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
1624 ) -> impl ::core::future::Future<Output = ()>;
1625
1626 #[doc = " Lock the bus.\n"]
1627 fn lock_bus(
1628 &mut self,
1629
1630 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
1631
1632 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
1633 ) -> impl ::core::future::Future<Output = ()>;
1634
1635 #[doc = " Unlock the bus.\n"]
1636 fn unlock_bus(
1637 &mut self,
1638
1639 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
1640
1641 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
1642 ) -> impl ::core::future::Future<Output = ()>;
1643
1644 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1645 fn register_vmo(
1646 &mut self,
1647
1648 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
1649
1650 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
1651 ) -> impl ::core::future::Future<Output = ()>;
1652
1653 fn unregister_vmo(
1654 &mut self,
1655
1656 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
1657
1658 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
1659 ) -> impl ::core::future::Future<Output = ()>;
1660
1661 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1662 fn release_registered_vmos(
1663 &mut self,
1664
1665 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
1666 ) -> impl ::core::future::Future<Output = ()>;
1667
1668 fn transmit_vmo(
1669 &mut self,
1670
1671 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
1672
1673 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
1674 ) -> impl ::core::future::Future<Output = ()>;
1675
1676 fn receive_vmo(
1677 &mut self,
1678
1679 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
1680
1681 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
1682 ) -> impl ::core::future::Future<Output = ()>;
1683
1684 fn exchange_vmo(
1685 &mut self,
1686
1687 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
1688
1689 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
1690 ) -> impl ::core::future::Future<Output = ()>;
1691}
1692
1693impl<___H, ___T> ::fidl_next::DispatchLocalServerMessage<___H, ___T> for SpiImpl
1694where
1695 ___H: SpiImplLocalServerHandler<___T>,
1696 ___T: ::fidl_next::Transport,
1697 for<'de> crate::wire::SpiImplTransmitVectorRequest<'de>: ::fidl_next::Decode<
1698 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1699 Constraint = (),
1700 >,
1701 for<'de> crate::wire::SpiImplReceiveVectorRequest: ::fidl_next::Decode<
1702 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1703 Constraint = (),
1704 >,
1705 for<'de> crate::wire::SpiImplExchangeVectorRequest<'de>: ::fidl_next::Decode<
1706 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1707 Constraint = (),
1708 >,
1709 for<'de> crate::wire::SpiImplLockBusRequest: ::fidl_next::Decode<
1710 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1711 Constraint = (),
1712 >,
1713 for<'de> crate::wire::SpiImplUnlockBusRequest: ::fidl_next::Decode<
1714 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1715 Constraint = (),
1716 >,
1717 for<'de> crate::wire::SpiImplRegisterVmoRequest: ::fidl_next::Decode<
1718 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1719 Constraint = (),
1720 >,
1721 for<'de> crate::wire::SpiImplUnregisterVmoRequest: ::fidl_next::Decode<
1722 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1723 Constraint = (),
1724 >,
1725 for<'de> crate::wire::SpiImplReleaseRegisteredVmosRequest: ::fidl_next::Decode<
1726 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1727 Constraint = (),
1728 >,
1729 for<'de> crate::wire::SpiImplTransmitVmoRequest: ::fidl_next::Decode<
1730 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1731 Constraint = (),
1732 >,
1733 for<'de> crate::wire::SpiImplReceiveVmoRequest: ::fidl_next::Decode<
1734 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1735 Constraint = (),
1736 >,
1737 for<'de> crate::wire::SpiImplExchangeVmoRequest: ::fidl_next::Decode<
1738 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1739 Constraint = (),
1740 >,
1741{
1742 async fn on_one_way(
1743 handler: &mut ___H,
1744 ordinal: u64,
1745 flexibility: ::fidl_next::protocol::Flexibility,
1746 body: ::fidl_next::Body<___T>,
1747 ) -> ::core::result::Result<
1748 (),
1749 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
1750 > {
1751 match ordinal {
1752 5302547493468731494 => match ::fidl_next::AsDecoderExt::into_decoded(body) {
1753 Ok(decoded) => {
1754 handler
1755 .release_registered_vmos(::fidl_next::Request::from_decoded(decoded))
1756 .await;
1757 Ok(())
1758 }
1759 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1760 ordinal: 5302547493468731494,
1761 error,
1762 }),
1763 },
1764
1765 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1766 }
1767 }
1768
1769 async fn on_two_way(
1770 handler: &mut ___H,
1771 ordinal: u64,
1772 flexibility: ::fidl_next::protocol::Flexibility,
1773 body: ::fidl_next::Body<___T>,
1774 responder: ::fidl_next::protocol::Responder<___T>,
1775 ) -> ::core::result::Result<
1776 (),
1777 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
1778 > {
1779 match ordinal {
1780 4261972386852856527 => {
1781 let responder = ::fidl_next::Responder::from_untyped(responder);
1782
1783 handler.get_chip_select_count(responder).await;
1784 Ok(())
1785 }
1786
1787 7287789131276374998 => {
1788 let responder = ::fidl_next::Responder::from_untyped(responder);
1789
1790 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1791 Ok(decoded) => {
1792 handler
1793 .transmit_vector(::fidl_next::Request::from_decoded(decoded), responder)
1794 .await;
1795 Ok(())
1796 }
1797 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1798 ordinal: 7287789131276374998,
1799 error,
1800 }),
1801 }
1802 }
1803
1804 4813495552606122700 => {
1805 let responder = ::fidl_next::Responder::from_untyped(responder);
1806
1807 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1808 Ok(decoded) => {
1809 handler
1810 .receive_vector(::fidl_next::Request::from_decoded(decoded), responder)
1811 .await;
1812 Ok(())
1813 }
1814 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1815 ordinal: 4813495552606122700,
1816 error,
1817 }),
1818 }
1819 }
1820
1821 3844617764012354164 => {
1822 let responder = ::fidl_next::Responder::from_untyped(responder);
1823
1824 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1825 Ok(decoded) => {
1826 handler
1827 .exchange_vector(::fidl_next::Request::from_decoded(decoded), responder)
1828 .await;
1829 Ok(())
1830 }
1831 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1832 ordinal: 3844617764012354164,
1833 error,
1834 }),
1835 }
1836 }
1837
1838 9187537331803160557 => {
1839 let responder = ::fidl_next::Responder::from_untyped(responder);
1840
1841 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1842 Ok(decoded) => {
1843 handler
1844 .lock_bus(::fidl_next::Request::from_decoded(decoded), responder)
1845 .await;
1846 Ok(())
1847 }
1848 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1849 ordinal: 9187537331803160557,
1850 error,
1851 }),
1852 }
1853 }
1854
1855 3150764477565251378 => {
1856 let responder = ::fidl_next::Responder::from_untyped(responder);
1857
1858 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1859 Ok(decoded) => {
1860 handler
1861 .unlock_bus(::fidl_next::Request::from_decoded(decoded), responder)
1862 .await;
1863 Ok(())
1864 }
1865 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1866 ordinal: 3150764477565251378,
1867 error,
1868 }),
1869 }
1870 }
1871
1872 2270783649342134233 => {
1873 let responder = ::fidl_next::Responder::from_untyped(responder);
1874
1875 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1876 Ok(decoded) => {
1877 handler
1878 .register_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1879 .await;
1880 Ok(())
1881 }
1882 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1883 ordinal: 2270783649342134233,
1884 error,
1885 }),
1886 }
1887 }
1888
1889 8778583385931240091 => {
1890 let responder = ::fidl_next::Responder::from_untyped(responder);
1891
1892 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1893 Ok(decoded) => {
1894 handler
1895 .unregister_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1896 .await;
1897 Ok(())
1898 }
1899 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1900 ordinal: 8778583385931240091,
1901 error,
1902 }),
1903 }
1904 }
1905
1906 1490935665662854691 => {
1907 let responder = ::fidl_next::Responder::from_untyped(responder);
1908
1909 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1910 Ok(decoded) => {
1911 handler
1912 .transmit_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1913 .await;
1914 Ok(())
1915 }
1916 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1917 ordinal: 1490935665662854691,
1918 error,
1919 }),
1920 }
1921 }
1922
1923 7091744647492940488 => {
1924 let responder = ::fidl_next::Responder::from_untyped(responder);
1925
1926 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1927 Ok(decoded) => {
1928 handler
1929 .receive_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1930 .await;
1931 Ok(())
1932 }
1933 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1934 ordinal: 7091744647492940488,
1935 error,
1936 }),
1937 }
1938 }
1939
1940 3592177641282126076 => {
1941 let responder = ::fidl_next::Responder::from_untyped(responder);
1942
1943 match ::fidl_next::AsDecoderExt::into_decoded(body) {
1944 Ok(decoded) => {
1945 handler
1946 .exchange_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1947 .await;
1948 Ok(())
1949 }
1950 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1951 ordinal: 3592177641282126076,
1952 error,
1953 }),
1954 }
1955 }
1956
1957 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1958 }
1959 }
1960}
1961
1962pub trait SpiImplClientHandler<
1966 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1967 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1968>
1969{
1970}
1971
1972impl<___H, ___T> ::fidl_next::DispatchClientMessage<___H, ___T> for SpiImpl
1973where
1974 ___H: SpiImplClientHandler<___T> + ::core::marker::Send,
1975 ___T: ::fidl_next::Transport,
1976{
1977 async fn on_event(
1978 handler: &mut ___H,
1979 ordinal: u64,
1980 flexibility: ::fidl_next::protocol::Flexibility,
1981 body: ::fidl_next::Body<___T>,
1982 ) -> ::core::result::Result<(), ::fidl_next::ProtocolError<___T::Error>> {
1983 match ordinal {
1984 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1985 }
1986 }
1987}
1988
1989pub trait SpiImplServerHandler<
1993 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1994 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1995>
1996{
1997 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
1998 fn get_chip_select_count(
1999 &mut self,
2000
2001 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
2002 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2003
2004 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
2005 fn transmit_vector(
2006 &mut self,
2007
2008 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
2009
2010 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
2011 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2012
2013 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
2014 fn receive_vector(
2015 &mut self,
2016
2017 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
2018
2019 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
2020 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2021
2022 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
2023 fn exchange_vector(
2024 &mut self,
2025
2026 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
2027
2028 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
2029 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2030
2031 #[doc = " Lock the bus.\n"]
2032 fn lock_bus(
2033 &mut self,
2034
2035 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
2036
2037 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
2038 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2039
2040 #[doc = " Unlock the bus.\n"]
2041 fn unlock_bus(
2042 &mut self,
2043
2044 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
2045
2046 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
2047 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2048
2049 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
2050 fn register_vmo(
2051 &mut self,
2052
2053 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
2054
2055 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
2056 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2057
2058 fn unregister_vmo(
2059 &mut self,
2060
2061 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
2062
2063 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
2064 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2065
2066 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
2067 fn release_registered_vmos(
2068 &mut self,
2069
2070 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
2071 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2072
2073 fn transmit_vmo(
2074 &mut self,
2075
2076 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
2077
2078 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
2079 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2080
2081 fn receive_vmo(
2082 &mut self,
2083
2084 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
2085
2086 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
2087 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2088
2089 fn exchange_vmo(
2090 &mut self,
2091
2092 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
2093
2094 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
2095 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2096}
2097
2098impl<___H, ___T> ::fidl_next::DispatchServerMessage<___H, ___T> for SpiImpl
2099where
2100 ___H: SpiImplServerHandler<___T> + ::core::marker::Send,
2101 ___T: ::fidl_next::Transport,
2102 for<'de> crate::wire::SpiImplTransmitVectorRequest<'de>: ::fidl_next::Decode<
2103 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2104 Constraint = (),
2105 >,
2106 for<'de> crate::wire::SpiImplReceiveVectorRequest: ::fidl_next::Decode<
2107 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2108 Constraint = (),
2109 >,
2110 for<'de> crate::wire::SpiImplExchangeVectorRequest<'de>: ::fidl_next::Decode<
2111 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2112 Constraint = (),
2113 >,
2114 for<'de> crate::wire::SpiImplLockBusRequest: ::fidl_next::Decode<
2115 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2116 Constraint = (),
2117 >,
2118 for<'de> crate::wire::SpiImplUnlockBusRequest: ::fidl_next::Decode<
2119 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2120 Constraint = (),
2121 >,
2122 for<'de> crate::wire::SpiImplRegisterVmoRequest: ::fidl_next::Decode<
2123 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2124 Constraint = (),
2125 >,
2126 for<'de> crate::wire::SpiImplUnregisterVmoRequest: ::fidl_next::Decode<
2127 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2128 Constraint = (),
2129 >,
2130 for<'de> crate::wire::SpiImplReleaseRegisteredVmosRequest: ::fidl_next::Decode<
2131 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2132 Constraint = (),
2133 >,
2134 for<'de> crate::wire::SpiImplTransmitVmoRequest: ::fidl_next::Decode<
2135 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2136 Constraint = (),
2137 >,
2138 for<'de> crate::wire::SpiImplReceiveVmoRequest: ::fidl_next::Decode<
2139 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2140 Constraint = (),
2141 >,
2142 for<'de> crate::wire::SpiImplExchangeVmoRequest: ::fidl_next::Decode<
2143 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2144 Constraint = (),
2145 >,
2146{
2147 async fn on_one_way(
2148 handler: &mut ___H,
2149 ordinal: u64,
2150 flexibility: ::fidl_next::protocol::Flexibility,
2151 body: ::fidl_next::Body<___T>,
2152 ) -> ::core::result::Result<
2153 (),
2154 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
2155 > {
2156 match ordinal {
2157 5302547493468731494 => match ::fidl_next::AsDecoderExt::into_decoded(body) {
2158 Ok(decoded) => {
2159 handler
2160 .release_registered_vmos(::fidl_next::Request::from_decoded(decoded))
2161 .await;
2162 Ok(())
2163 }
2164 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2165 ordinal: 5302547493468731494,
2166 error,
2167 }),
2168 },
2169
2170 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2171 }
2172 }
2173
2174 async fn on_two_way(
2175 handler: &mut ___H,
2176 ordinal: u64,
2177 flexibility: ::fidl_next::protocol::Flexibility,
2178 body: ::fidl_next::Body<___T>,
2179 responder: ::fidl_next::protocol::Responder<___T>,
2180 ) -> ::core::result::Result<
2181 (),
2182 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
2183 > {
2184 match ordinal {
2185 4261972386852856527 => {
2186 let responder = ::fidl_next::Responder::from_untyped(responder);
2187
2188 handler.get_chip_select_count(responder).await;
2189 Ok(())
2190 }
2191
2192 7287789131276374998 => {
2193 let responder = ::fidl_next::Responder::from_untyped(responder);
2194
2195 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2196 Ok(decoded) => {
2197 handler
2198 .transmit_vector(::fidl_next::Request::from_decoded(decoded), responder)
2199 .await;
2200 Ok(())
2201 }
2202 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2203 ordinal: 7287789131276374998,
2204 error,
2205 }),
2206 }
2207 }
2208
2209 4813495552606122700 => {
2210 let responder = ::fidl_next::Responder::from_untyped(responder);
2211
2212 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2213 Ok(decoded) => {
2214 handler
2215 .receive_vector(::fidl_next::Request::from_decoded(decoded), responder)
2216 .await;
2217 Ok(())
2218 }
2219 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2220 ordinal: 4813495552606122700,
2221 error,
2222 }),
2223 }
2224 }
2225
2226 3844617764012354164 => {
2227 let responder = ::fidl_next::Responder::from_untyped(responder);
2228
2229 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2230 Ok(decoded) => {
2231 handler
2232 .exchange_vector(::fidl_next::Request::from_decoded(decoded), responder)
2233 .await;
2234 Ok(())
2235 }
2236 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2237 ordinal: 3844617764012354164,
2238 error,
2239 }),
2240 }
2241 }
2242
2243 9187537331803160557 => {
2244 let responder = ::fidl_next::Responder::from_untyped(responder);
2245
2246 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2247 Ok(decoded) => {
2248 handler
2249 .lock_bus(::fidl_next::Request::from_decoded(decoded), responder)
2250 .await;
2251 Ok(())
2252 }
2253 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2254 ordinal: 9187537331803160557,
2255 error,
2256 }),
2257 }
2258 }
2259
2260 3150764477565251378 => {
2261 let responder = ::fidl_next::Responder::from_untyped(responder);
2262
2263 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2264 Ok(decoded) => {
2265 handler
2266 .unlock_bus(::fidl_next::Request::from_decoded(decoded), responder)
2267 .await;
2268 Ok(())
2269 }
2270 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2271 ordinal: 3150764477565251378,
2272 error,
2273 }),
2274 }
2275 }
2276
2277 2270783649342134233 => {
2278 let responder = ::fidl_next::Responder::from_untyped(responder);
2279
2280 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2281 Ok(decoded) => {
2282 handler
2283 .register_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2284 .await;
2285 Ok(())
2286 }
2287 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2288 ordinal: 2270783649342134233,
2289 error,
2290 }),
2291 }
2292 }
2293
2294 8778583385931240091 => {
2295 let responder = ::fidl_next::Responder::from_untyped(responder);
2296
2297 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2298 Ok(decoded) => {
2299 handler
2300 .unregister_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2301 .await;
2302 Ok(())
2303 }
2304 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2305 ordinal: 8778583385931240091,
2306 error,
2307 }),
2308 }
2309 }
2310
2311 1490935665662854691 => {
2312 let responder = ::fidl_next::Responder::from_untyped(responder);
2313
2314 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2315 Ok(decoded) => {
2316 handler
2317 .transmit_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2318 .await;
2319 Ok(())
2320 }
2321 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2322 ordinal: 1490935665662854691,
2323 error,
2324 }),
2325 }
2326 }
2327
2328 7091744647492940488 => {
2329 let responder = ::fidl_next::Responder::from_untyped(responder);
2330
2331 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2332 Ok(decoded) => {
2333 handler
2334 .receive_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2335 .await;
2336 Ok(())
2337 }
2338 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2339 ordinal: 7091744647492940488,
2340 error,
2341 }),
2342 }
2343 }
2344
2345 3592177641282126076 => {
2346 let responder = ::fidl_next::Responder::from_untyped(responder);
2347
2348 match ::fidl_next::AsDecoderExt::into_decoded(body) {
2349 Ok(decoded) => {
2350 handler
2351 .exchange_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2352 .await;
2353 Ok(())
2354 }
2355 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2356 ordinal: 3592177641282126076,
2357 error,
2358 }),
2359 }
2360 }
2361
2362 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2363 }
2364 }
2365}
2366
2367impl<___T> SpiImplClientHandler<___T> for ::fidl_next::IgnoreEvents where
2368 ___T: ::fidl_next::Transport
2369{
2370}
2371
2372impl<___H, ___T> SpiImplLocalClientHandler<___T> for ::fidl_next::Local<___H>
2373where
2374 ___H: SpiImplClientHandler<___T>,
2375 ___T: ::fidl_next::Transport,
2376{
2377}
2378
2379impl<___H, ___T> SpiImplLocalServerHandler<___T> for ::fidl_next::Local<___H>
2380where
2381 ___H: SpiImplServerHandler<___T>,
2382 ___T: ::fidl_next::Transport,
2383{
2384 async fn get_chip_select_count(
2385 &mut self,
2386
2387 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
2388 ) {
2389 ___H::get_chip_select_count(&mut self.0, responder).await
2390 }
2391
2392 async fn transmit_vector(
2393 &mut self,
2394
2395 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
2396
2397 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
2398 ) {
2399 ___H::transmit_vector(&mut self.0, request, responder).await
2400 }
2401
2402 async fn receive_vector(
2403 &mut self,
2404
2405 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
2406
2407 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
2408 ) {
2409 ___H::receive_vector(&mut self.0, request, responder).await
2410 }
2411
2412 async fn exchange_vector(
2413 &mut self,
2414
2415 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
2416
2417 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
2418 ) {
2419 ___H::exchange_vector(&mut self.0, request, responder).await
2420 }
2421
2422 async fn lock_bus(
2423 &mut self,
2424
2425 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
2426
2427 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
2428 ) {
2429 ___H::lock_bus(&mut self.0, request, responder).await
2430 }
2431
2432 async fn unlock_bus(
2433 &mut self,
2434
2435 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
2436
2437 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
2438 ) {
2439 ___H::unlock_bus(&mut self.0, request, responder).await
2440 }
2441
2442 async fn register_vmo(
2443 &mut self,
2444
2445 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
2446
2447 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
2448 ) {
2449 ___H::register_vmo(&mut self.0, request, responder).await
2450 }
2451
2452 async fn unregister_vmo(
2453 &mut self,
2454
2455 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
2456
2457 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
2458 ) {
2459 ___H::unregister_vmo(&mut self.0, request, responder).await
2460 }
2461
2462 async fn release_registered_vmos(
2463 &mut self,
2464
2465 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
2466 ) {
2467 ___H::release_registered_vmos(&mut self.0, request).await
2468 }
2469
2470 async fn transmit_vmo(
2471 &mut self,
2472
2473 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
2474
2475 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
2476 ) {
2477 ___H::transmit_vmo(&mut self.0, request, responder).await
2478 }
2479
2480 async fn receive_vmo(
2481 &mut self,
2482
2483 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
2484
2485 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
2486 ) {
2487 ___H::receive_vmo(&mut self.0, request, responder).await
2488 }
2489
2490 async fn exchange_vmo(
2491 &mut self,
2492
2493 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
2494
2495 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
2496 ) {
2497 ___H::exchange_vmo(&mut self.0, request, responder).await
2498 }
2499}
2500
2501pub use fidl_next_common_fuchsia_hardware_spiimpl::*;