1#![warn(clippy::all)]
3#![allow(unused_parens, unused_variables, unused_mut, unused_imports, unreachable_code)]
4
5pub mod natural {
6
7 pub use fidl_next_common_fuchsia_hardware_spiimpl::natural::*;
8
9 #[derive(Debug, PartialEq)]
10 pub struct SpiImplRegisterVmoRequest {
11 pub chip_select: u32,
12
13 pub vmo_id: u32,
14
15 pub vmo: ::fidl_next_fuchsia_mem::natural::Range,
16
17 pub rights: ::fidl_next_fuchsia_hardware_sharedmemory::natural::SharedVmoRight,
18 }
19
20 unsafe impl<___E> ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>
21 for SpiImplRegisterVmoRequest
22 where
23 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
24 ___E: ::fidl_next::fuchsia::HandleEncoder,
25 {
26 #[inline]
27 fn encode(
28 self,
29 encoder_: &mut ___E,
30 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplRegisterVmoRequest>,
31 _: (),
32 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
33 ::fidl_next::munge! {
34 let crate::wire::SpiImplRegisterVmoRequest {
35 chip_select,
36 vmo_id,
37 vmo,
38 rights,
39
40 } = out_;
41 }
42
43 ::fidl_next::Encode::encode(self.chip_select, encoder_, chip_select, ())?;
44
45 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(chip_select.as_mut_ptr()) };
46
47 ::fidl_next::Encode::encode(self.vmo_id, encoder_, vmo_id, ())?;
48
49 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo_id.as_mut_ptr()) };
50
51 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
52
53 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo.as_mut_ptr()) };
54
55 ::fidl_next::Encode::encode(self.rights, encoder_, rights, ())?;
56
57 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(rights.as_mut_ptr()) };
58
59 Ok(())
60 }
61 }
62
63 unsafe impl<___E>
64 ::fidl_next::EncodeOption<
65 ::fidl_next::wire::Box<'static, crate::wire::SpiImplRegisterVmoRequest>,
66 ___E,
67 > for SpiImplRegisterVmoRequest
68 where
69 ___E: ::fidl_next::Encoder + ?Sized,
70 SpiImplRegisterVmoRequest:
71 ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>,
72 {
73 #[inline]
74 fn encode_option(
75 this: ::core::option::Option<Self>,
76 encoder: &mut ___E,
77 out: &mut ::core::mem::MaybeUninit<
78 ::fidl_next::wire::Box<'static, crate::wire::SpiImplRegisterVmoRequest>,
79 >,
80 _: (),
81 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
82 if let Some(inner) = this {
83 ::fidl_next::EncoderExt::encode_next(encoder, inner)?;
84 ::fidl_next::wire::Box::encode_present(out);
85 } else {
86 ::fidl_next::wire::Box::encode_absent(out);
87 }
88
89 Ok(())
90 }
91 }
92
93 impl ::fidl_next::FromWire<crate::wire::SpiImplRegisterVmoRequest> for SpiImplRegisterVmoRequest {
94 #[inline]
95 fn from_wire(wire: crate::wire::SpiImplRegisterVmoRequest) -> Self {
96 Self {
97 chip_select: ::fidl_next::FromWire::from_wire(wire.chip_select),
98
99 vmo_id: ::fidl_next::FromWire::from_wire(wire.vmo_id),
100
101 vmo: ::fidl_next::FromWire::from_wire(wire.vmo),
102
103 rights: ::fidl_next::FromWire::from_wire(wire.rights),
104 }
105 }
106 }
107
108 #[derive(Debug, PartialEq)]
109 #[repr(C)]
110 pub struct SpiImplUnregisterVmoResponse {
111 pub vmo: ::fidl_next::fuchsia::zx::Vmo,
112 }
113
114 unsafe impl<___E> ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>
115 for SpiImplUnregisterVmoResponse
116 where
117 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
118 ___E: ::fidl_next::fuchsia::HandleEncoder,
119 {
120 const COPY_OPTIMIZATION: ::fidl_next::CopyOptimization<
121 Self,
122 crate::wire::SpiImplUnregisterVmoResponse,
123 > = unsafe {
124 ::fidl_next::CopyOptimization::enable_if(
125 true && <::fidl_next::fuchsia::zx::Vmo as ::fidl_next::Encode<
126 ::fidl_next::wire::fuchsia::Vmo,
127 ___E,
128 >>::COPY_OPTIMIZATION
129 .is_enabled(),
130 )
131 };
132
133 #[inline]
134 fn encode(
135 self,
136 encoder_: &mut ___E,
137 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplUnregisterVmoResponse>,
138 _: (),
139 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
140 ::fidl_next::munge! {
141 let crate::wire::SpiImplUnregisterVmoResponse {
142 vmo,
143
144 } = out_;
145 }
146
147 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
148
149 let mut _field = unsafe { ::fidl_next::Slot::new_unchecked(vmo.as_mut_ptr()) };
150
151 Ok(())
152 }
153 }
154
155 unsafe impl<___E>
156 ::fidl_next::EncodeOption<
157 ::fidl_next::wire::Box<'static, crate::wire::SpiImplUnregisterVmoResponse>,
158 ___E,
159 > for SpiImplUnregisterVmoResponse
160 where
161 ___E: ::fidl_next::Encoder + ?Sized,
162 SpiImplUnregisterVmoResponse:
163 ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>,
164 {
165 #[inline]
166 fn encode_option(
167 this: ::core::option::Option<Self>,
168 encoder: &mut ___E,
169 out: &mut ::core::mem::MaybeUninit<
170 ::fidl_next::wire::Box<'static, crate::wire::SpiImplUnregisterVmoResponse>,
171 >,
172 _: (),
173 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
174 if let Some(inner) = this {
175 ::fidl_next::EncoderExt::encode_next(encoder, inner)?;
176 ::fidl_next::wire::Box::encode_present(out);
177 } else {
178 ::fidl_next::wire::Box::encode_absent(out);
179 }
180
181 Ok(())
182 }
183 }
184
185 impl ::fidl_next::FromWire<crate::wire::SpiImplUnregisterVmoResponse>
186 for SpiImplUnregisterVmoResponse
187 {
188 const COPY_OPTIMIZATION: ::fidl_next::CopyOptimization<
189 crate::wire::SpiImplUnregisterVmoResponse,
190 Self,
191 > = unsafe {
192 ::fidl_next::CopyOptimization::enable_if(
193 true && <::fidl_next::fuchsia::zx::Vmo as ::fidl_next::FromWire<
194 ::fidl_next::wire::fuchsia::Vmo,
195 >>::COPY_OPTIMIZATION
196 .is_enabled(),
197 )
198 };
199
200 #[inline]
201 fn from_wire(wire: crate::wire::SpiImplUnregisterVmoResponse) -> Self {
202 Self { vmo: ::fidl_next::FromWire::from_wire(wire.vmo) }
203 }
204 }
205}
206
207pub mod wire {
208
209 pub use fidl_next_common_fuchsia_hardware_spiimpl::wire::*;
210
211 #[derive(Debug)]
213 #[repr(C)]
214 pub struct SpiImplRegisterVmoRequest {
215 pub chip_select: ::fidl_next::wire::Uint32,
216
217 pub vmo_id: ::fidl_next::wire::Uint32,
218
219 pub vmo: ::fidl_next_fuchsia_mem::wire::Range,
220
221 pub rights: ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
222 }
223
224 static_assertions::const_assert_eq!(std::mem::size_of::<SpiImplRegisterVmoRequest>(), 40);
225 static_assertions::const_assert_eq!(std::mem::align_of::<SpiImplRegisterVmoRequest>(), 8);
226
227 static_assertions::const_assert_eq!(
228 std::mem::offset_of!(SpiImplRegisterVmoRequest, chip_select),
229 0
230 );
231
232 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplRegisterVmoRequest, vmo_id), 4);
233
234 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplRegisterVmoRequest, vmo), 8);
235
236 static_assertions::const_assert_eq!(
237 std::mem::offset_of!(SpiImplRegisterVmoRequest, rights),
238 32
239 );
240
241 impl ::fidl_next::Constrained for SpiImplRegisterVmoRequest {
242 type Constraint = ();
243
244 fn validate(
245 _: ::fidl_next::Slot<'_, Self>,
246 _: Self::Constraint,
247 ) -> Result<(), ::fidl_next::ValidationError> {
248 Ok(())
249 }
250 }
251
252 unsafe impl ::fidl_next::Wire for SpiImplRegisterVmoRequest {
253 type Narrowed<'de> = SpiImplRegisterVmoRequest;
254
255 #[inline]
256 fn zero_padding(out_: &mut ::core::mem::MaybeUninit<Self>) {
257 ::fidl_next::munge! {
258 let Self {
259 chip_select,
260 vmo_id,
261 vmo,
262 rights,
263
264 } = &mut *out_;
265 }
266
267 ::fidl_next::Wire::zero_padding(chip_select);
268
269 ::fidl_next::Wire::zero_padding(vmo_id);
270
271 ::fidl_next::Wire::zero_padding(vmo);
272
273 ::fidl_next::Wire::zero_padding(rights);
274
275 unsafe {
276 out_.as_mut_ptr().cast::<u8>().add(36).write_bytes(0, 4);
277 }
278 }
279 }
280
281 unsafe impl<___D> ::fidl_next::Decode<___D> for SpiImplRegisterVmoRequest
282 where
283 ___D: ::fidl_next::decoder::InternalHandleDecoder + ?Sized,
284 ___D: ::fidl_next::fuchsia::HandleDecoder,
285 {
286 fn decode(
287 slot_: ::fidl_next::Slot<'_, Self>,
288 decoder_: &mut ___D,
289 _: (),
290 ) -> ::core::result::Result<(), ::fidl_next::DecodeError> {
291 if slot_.as_bytes()[36..40] != [0u8; 4] {
292 return Err(::fidl_next::DecodeError::InvalidPadding);
293 }
294
295 ::fidl_next::munge! {
296 let Self {
297 mut chip_select,
298 mut vmo_id,
299 mut vmo,
300 mut rights,
301
302 } = slot_;
303 }
304
305 let _field = chip_select.as_mut();
306
307 ::fidl_next::Decode::decode(chip_select.as_mut(), decoder_, ())?;
308
309 let _field = vmo_id.as_mut();
310
311 ::fidl_next::Decode::decode(vmo_id.as_mut(), decoder_, ())?;
312
313 let _field = vmo.as_mut();
314
315 ::fidl_next::Decode::decode(vmo.as_mut(), decoder_, ())?;
316
317 let _field = rights.as_mut();
318
319 ::fidl_next::Decode::decode(rights.as_mut(), decoder_, ())?;
320
321 Ok(())
322 }
323 }
324
325 impl ::fidl_next::IntoNatural for SpiImplRegisterVmoRequest {
326 type Natural = crate::natural::SpiImplRegisterVmoRequest;
327 }
328
329 #[derive(Debug)]
331 #[repr(C)]
332 pub struct SpiImplUnregisterVmoResponse {
333 pub vmo: ::fidl_next::wire::fuchsia::Vmo,
334 }
335
336 static_assertions::const_assert_eq!(std::mem::size_of::<SpiImplUnregisterVmoResponse>(), 4);
337 static_assertions::const_assert_eq!(std::mem::align_of::<SpiImplUnregisterVmoResponse>(), 4);
338
339 static_assertions::const_assert_eq!(std::mem::offset_of!(SpiImplUnregisterVmoResponse, vmo), 0);
340
341 impl ::fidl_next::Constrained for SpiImplUnregisterVmoResponse {
342 type Constraint = ();
343
344 fn validate(
345 _: ::fidl_next::Slot<'_, Self>,
346 _: Self::Constraint,
347 ) -> Result<(), ::fidl_next::ValidationError> {
348 Ok(())
349 }
350 }
351
352 unsafe impl ::fidl_next::Wire for SpiImplUnregisterVmoResponse {
353 type Narrowed<'de> = SpiImplUnregisterVmoResponse;
354
355 #[inline]
356 fn zero_padding(out_: &mut ::core::mem::MaybeUninit<Self>) {
357 ::fidl_next::munge! {
358 let Self {
359 vmo,
360
361 } = &mut *out_;
362 }
363
364 ::fidl_next::Wire::zero_padding(vmo);
365 }
366 }
367
368 unsafe impl<___D> ::fidl_next::Decode<___D> for SpiImplUnregisterVmoResponse
369 where
370 ___D: ::fidl_next::decoder::InternalHandleDecoder + ?Sized,
371 ___D: ::fidl_next::fuchsia::HandleDecoder,
372 {
373 fn decode(
374 slot_: ::fidl_next::Slot<'_, Self>,
375 decoder_: &mut ___D,
376 _: (),
377 ) -> ::core::result::Result<(), ::fidl_next::DecodeError> {
378 ::fidl_next::munge! {
379 let Self {
380 mut vmo,
381
382 } = slot_;
383 }
384
385 let _field = vmo.as_mut();
386
387 ::fidl_next::Decode::decode(vmo.as_mut(), decoder_, ())?;
388
389 Ok(())
390 }
391 }
392
393 impl ::fidl_next::IntoNatural for SpiImplUnregisterVmoResponse {
394 type Natural = crate::natural::SpiImplUnregisterVmoResponse;
395 }
396}
397
398pub mod wire_optional {
399
400 pub use fidl_next_common_fuchsia_hardware_spiimpl::wire_optional::*;
401}
402
403pub mod generic {
404
405 pub use fidl_next_common_fuchsia_hardware_spiimpl::generic::*;
406
407 pub struct SpiImplRegisterVmoRequest<T0, T1, T2, T3> {
409 pub chip_select: T0,
410
411 pub vmo_id: T1,
412
413 pub vmo: T2,
414
415 pub rights: T3,
416 }
417
418 unsafe impl<___E, T0, T1, T2, T3>
419 ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>
420 for SpiImplRegisterVmoRequest<T0, T1, T2, T3>
421 where
422 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
423 ___E: ::fidl_next::fuchsia::HandleEncoder,
424 T0: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
425 T1: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
426 T2: ::fidl_next::Encode<::fidl_next_fuchsia_mem::wire::Range, ___E>,
427 T3: ::fidl_next::Encode<
428 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
429 ___E,
430 >,
431 {
432 #[inline]
433 fn encode(
434 self,
435 encoder_: &mut ___E,
436 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplRegisterVmoRequest>,
437 _: (),
438 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
439 ::fidl_next::munge! {
440 let crate::wire::SpiImplRegisterVmoRequest {
441 chip_select,
442 vmo_id,
443 vmo,
444 rights,
445
446 } = out_;
447 }
448
449 ::fidl_next::Encode::encode(self.chip_select, encoder_, chip_select, ())?;
450
451 ::fidl_next::Encode::encode(self.vmo_id, encoder_, vmo_id, ())?;
452
453 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
454
455 ::fidl_next::Encode::encode(self.rights, encoder_, rights, ())?;
456
457 Ok(())
458 }
459 }
460
461 unsafe impl<'a, ___E, T0, T1, T2, T3>
462 ::fidl_next::Encode<crate::wire::SpiImplRegisterVmoRequest, ___E>
463 for &'a SpiImplRegisterVmoRequest<T0, T1, T2, T3>
464 where
465 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
466 ___E: ::fidl_next::fuchsia::HandleEncoder,
467 &'a T0: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
468 &'a T1: ::fidl_next::Encode<::fidl_next::wire::Uint32, ___E>,
469 &'a T2: ::fidl_next::Encode<::fidl_next_fuchsia_mem::wire::Range, ___E>,
470 &'a T3: ::fidl_next::Encode<
471 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
472 ___E,
473 >,
474 {
475 #[inline]
476 fn encode(
477 self,
478 encoder_: &mut ___E,
479 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplRegisterVmoRequest>,
480 _: (),
481 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
482 ::fidl_next::munge! {
483 let crate::wire::SpiImplRegisterVmoRequest {
484 chip_select,
485 vmo_id,
486 vmo,
487 rights,
488
489 } = out_;
490 }
491
492 ::fidl_next::Encode::encode(&self.chip_select, encoder_, chip_select, ())?;
493
494 ::fidl_next::Encode::encode(&self.vmo_id, encoder_, vmo_id, ())?;
495
496 ::fidl_next::Encode::encode(&self.vmo, encoder_, vmo, ())?;
497
498 ::fidl_next::Encode::encode(&self.rights, encoder_, rights, ())?;
499
500 Ok(())
501 }
502 }
503
504 pub struct SpiImplUnregisterVmoResponse<T0> {
506 pub vmo: T0,
507 }
508
509 unsafe impl<___E, T0> ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>
510 for SpiImplUnregisterVmoResponse<T0>
511 where
512 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
513 ___E: ::fidl_next::fuchsia::HandleEncoder,
514 T0: ::fidl_next::Encode<::fidl_next::wire::fuchsia::Vmo, ___E>,
515 {
516 #[inline]
517 fn encode(
518 self,
519 encoder_: &mut ___E,
520 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplUnregisterVmoResponse>,
521 _: (),
522 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
523 ::fidl_next::munge! {
524 let crate::wire::SpiImplUnregisterVmoResponse {
525 vmo,
526
527 } = out_;
528 }
529
530 ::fidl_next::Encode::encode(self.vmo, encoder_, vmo, ())?;
531
532 Ok(())
533 }
534 }
535
536 unsafe impl<'a, ___E, T0> ::fidl_next::Encode<crate::wire::SpiImplUnregisterVmoResponse, ___E>
537 for &'a SpiImplUnregisterVmoResponse<T0>
538 where
539 ___E: ::fidl_next::encoder::InternalHandleEncoder + ?Sized,
540 ___E: ::fidl_next::fuchsia::HandleEncoder,
541 &'a T0: ::fidl_next::Encode<::fidl_next::wire::fuchsia::Vmo, ___E>,
542 {
543 #[inline]
544 fn encode(
545 self,
546 encoder_: &mut ___E,
547 out_: &mut ::core::mem::MaybeUninit<crate::wire::SpiImplUnregisterVmoResponse>,
548 _: (),
549 ) -> ::core::result::Result<(), ::fidl_next::EncodeError> {
550 ::fidl_next::munge! {
551 let crate::wire::SpiImplUnregisterVmoResponse {
552 vmo,
553
554 } = out_;
555 }
556
557 ::fidl_next::Encode::encode(&self.vmo, encoder_, vmo, ())?;
558
559 Ok(())
560 }
561 }
562}
563
564pub use self::natural::*;
565
566#[derive(Debug)]
568pub struct Service;
569
570impl ::fidl_next::DiscoverableService for Service {
571 const SERVICE_NAME: &'static str = "fuchsia.hardware.spiimpl.Service";
572 const MEMBER_NAMES: &'static [&'static str] = &["device"];
573}
574
575impl ::fidl_next::HasServiceRequest<::fdf_fidl::DriverChannel> for Service {}
576
577impl<___C> ::fidl_next::Service<___C> for Service
578where
579 ___C: ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>,
580{
581 type Connector = ServiceConnector<___C>;
582}
583
584#[repr(transparent)]
586pub struct ServiceConnector<___C> {
587 #[allow(dead_code)]
588 connector: ___C,
589}
590
591impl<___C> ServiceConnector<___C>
592where
593 ___C: ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>,
594{
595 pub fn device(
597 &self,
598 server_end: ::fidl_next::ServerEnd<crate::SpiImpl, ::fdf_fidl::DriverChannel>,
599 ) -> ::core::result::Result<
600 (),
601 <___C as ::fidl_next::protocol::ServiceConnector<::fdf_fidl::DriverChannel>>::Error,
602 > {
603 ::fidl_next::protocol::ServiceConnector::<::fdf_fidl::DriverChannel>::connect_to_member(
604 &self.connector,
605 "device",
606 server_end.into_untyped(),
607 )
608 }
609}
610
611pub trait ServiceHandler {
613 fn device(&self, server_end: ::fidl_next::ServerEnd<crate::SpiImpl, ::fdf_fidl::DriverChannel>);
615}
616
617impl<___H, ___T> ::fidl_next::DispatchServiceHandler<___H, ___T> for Service
618where
619 ___H: ServiceHandler,
620 ::fdf_fidl::DriverChannel: ::fidl_next::InstanceFromServiceTransport<___T>,
621{
622 fn on_connection(handler: &___H, member: &str, server_end: ___T) {
623 use ::fidl_next::InstanceFromServiceTransport;
624 match member {
625 "device" => handler.device(::fidl_next::ServerEnd::from_untyped(
626 ::fdf_fidl::DriverChannel::from_service_transport(server_end),
627 )),
628
629 _ => unreachable!(),
630 }
631 }
632}
633
634#[doc = " Low-level protocol for spi drivers.\n"]
636#[derive(PartialEq, Debug)]
637pub struct SpiImpl;
638
639impl ::fidl_next::Discoverable for SpiImpl {
640 const PROTOCOL_NAME: &'static str = "fuchsia.hardware.spiimpl.SpiImpl";
641}
642
643#[cfg(feature = "driver")]
644impl ::fidl_next::HasTransport for SpiImpl {
645 type Transport = ::fdf_fidl::DriverChannel;
646}
647
648pub mod spi_impl {
649 pub mod prelude {
650 pub use crate::{
651 SpiImpl, SpiImplClientHandler, SpiImplLocalClientHandler, SpiImplLocalServerHandler,
652 SpiImplServerHandler, spi_impl,
653 };
654
655 pub use crate::natural::SpiImplExchangeVectorRequest;
656
657 pub use crate::natural::SpiImplExchangeVmoRequest;
658
659 pub use crate::natural::SpiImplGetChipSelectCountResponse;
660
661 pub use crate::natural::SpiImplLockBusRequest;
662
663 pub use crate::natural::SpiImplReceiveVectorRequest;
664
665 pub use crate::natural::SpiImplReceiveVmoRequest;
666
667 pub use crate::natural::SpiImplRegisterVmoRequest;
668
669 pub use crate::natural::SpiImplReleaseRegisteredVmosRequest;
670
671 pub use crate::natural::SpiImplTransmitVectorRequest;
672
673 pub use crate::natural::SpiImplTransmitVmoRequest;
674
675 pub use crate::natural::SpiImplUnlockBusRequest;
676
677 pub use crate::natural::SpiImplUnregisterVmoRequest;
678
679 pub use crate::natural::SpiImplExchangeVectorResponse;
680
681 pub use crate::natural::SpiImplExchangeVmoResponse;
682
683 pub use crate::natural::SpiImplLockBusResponse;
684
685 pub use crate::natural::SpiImplReceiveVectorResponse;
686
687 pub use crate::natural::SpiImplReceiveVmoResponse;
688
689 pub use crate::natural::SpiImplRegisterVmoResponse;
690
691 pub use crate::natural::SpiImplTransmitVectorResponse;
692
693 pub use crate::natural::SpiImplTransmitVmoResponse;
694
695 pub use crate::natural::SpiImplUnlockBusResponse;
696
697 pub use crate::natural::SpiImplUnregisterVmoResponse;
698 }
699
700 pub struct GetChipSelectCount;
701
702 impl ::fidl_next::Method for GetChipSelectCount {
703 const ORDINAL: u64 = 4261972386852856527;
704 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
705 ::fidl_next::protocol::Flexibility::Strict;
706
707 type Protocol = crate::SpiImpl;
708
709 type Request = ::fidl_next::wire::EmptyMessageBody;
710 }
711
712 impl ::fidl_next::TwoWayMethod for GetChipSelectCount {
713 type Response = ::fidl_next::wire::Strict<crate::wire::SpiImplGetChipSelectCountResponse>;
714 }
715
716 impl<___R> ::fidl_next::Respond<___R> for GetChipSelectCount {
717 type Output = ::fidl_next::Strict<crate::generic::SpiImplGetChipSelectCountResponse<___R>>;
718
719 fn respond(response: ___R) -> Self::Output {
720 ::fidl_next::Strict(crate::generic::SpiImplGetChipSelectCountResponse {
721 count: response,
722 })
723 }
724 }
725
726 pub struct TransmitVector;
727
728 impl ::fidl_next::Method for TransmitVector {
729 const ORDINAL: u64 = 7287789131276374998;
730 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
731 ::fidl_next::protocol::Flexibility::Strict;
732
733 type Protocol = crate::SpiImpl;
734
735 type Request = crate::wire::SpiImplTransmitVectorRequest<'static>;
736 }
737
738 impl ::fidl_next::TwoWayMethod for TransmitVector {
739 type Response = ::fidl_next::wire::Result<
740 'static,
741 crate::wire::SpiImplTransmitVectorResponse,
742 ::fidl_next::wire::fuchsia::Status,
743 >;
744 }
745
746 impl<___R> ::fidl_next::Respond<___R> for TransmitVector {
747 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
748
749 fn respond(response: ___R) -> Self::Output {
750 ::core::result::Result::Ok(response)
751 }
752 }
753
754 impl<___R> ::fidl_next::RespondErr<___R> for TransmitVector {
755 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
756
757 fn respond_err(response: ___R) -> Self::Output {
758 ::core::result::Result::Err(response)
759 }
760 }
761
762 pub struct ReceiveVector;
763
764 impl ::fidl_next::Method for ReceiveVector {
765 const ORDINAL: u64 = 4813495552606122700;
766 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
767 ::fidl_next::protocol::Flexibility::Strict;
768
769 type Protocol = crate::SpiImpl;
770
771 type Request = crate::wire::SpiImplReceiveVectorRequest;
772 }
773
774 impl ::fidl_next::TwoWayMethod for ReceiveVector {
775 type Response = ::fidl_next::wire::Result<
776 'static,
777 crate::wire::SpiImplReceiveVectorResponse<'static>,
778 ::fidl_next::wire::fuchsia::Status,
779 >;
780 }
781
782 impl<___R> ::fidl_next::Respond<___R> for ReceiveVector {
783 type Output = ::core::result::Result<
784 crate::generic::SpiImplReceiveVectorResponse<___R>,
785 ::fidl_next::never::Never,
786 >;
787
788 fn respond(response: ___R) -> Self::Output {
789 ::core::result::Result::Ok(crate::generic::SpiImplReceiveVectorResponse {
790 data: response,
791 })
792 }
793 }
794
795 impl<___R> ::fidl_next::RespondErr<___R> for ReceiveVector {
796 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
797
798 fn respond_err(response: ___R) -> Self::Output {
799 ::core::result::Result::Err(response)
800 }
801 }
802
803 pub struct ExchangeVector;
804
805 impl ::fidl_next::Method for ExchangeVector {
806 const ORDINAL: u64 = 3844617764012354164;
807 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
808 ::fidl_next::protocol::Flexibility::Strict;
809
810 type Protocol = crate::SpiImpl;
811
812 type Request = crate::wire::SpiImplExchangeVectorRequest<'static>;
813 }
814
815 impl ::fidl_next::TwoWayMethod for ExchangeVector {
816 type Response = ::fidl_next::wire::Result<
817 'static,
818 crate::wire::SpiImplExchangeVectorResponse<'static>,
819 ::fidl_next::wire::fuchsia::Status,
820 >;
821 }
822
823 impl<___R> ::fidl_next::Respond<___R> for ExchangeVector {
824 type Output = ::core::result::Result<
825 crate::generic::SpiImplExchangeVectorResponse<___R>,
826 ::fidl_next::never::Never,
827 >;
828
829 fn respond(response: ___R) -> Self::Output {
830 ::core::result::Result::Ok(crate::generic::SpiImplExchangeVectorResponse {
831 rxdata: response,
832 })
833 }
834 }
835
836 impl<___R> ::fidl_next::RespondErr<___R> for ExchangeVector {
837 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
838
839 fn respond_err(response: ___R) -> Self::Output {
840 ::core::result::Result::Err(response)
841 }
842 }
843
844 pub struct LockBus;
845
846 impl ::fidl_next::Method for LockBus {
847 const ORDINAL: u64 = 9187537331803160557;
848 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
849 ::fidl_next::protocol::Flexibility::Strict;
850
851 type Protocol = crate::SpiImpl;
852
853 type Request = crate::wire::SpiImplLockBusRequest;
854 }
855
856 impl ::fidl_next::TwoWayMethod for LockBus {
857 type Response = ::fidl_next::wire::Result<
858 'static,
859 crate::wire::SpiImplLockBusResponse,
860 ::fidl_next::wire::fuchsia::Status,
861 >;
862 }
863
864 impl<___R> ::fidl_next::Respond<___R> for LockBus {
865 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
866
867 fn respond(response: ___R) -> Self::Output {
868 ::core::result::Result::Ok(response)
869 }
870 }
871
872 impl<___R> ::fidl_next::RespondErr<___R> for LockBus {
873 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
874
875 fn respond_err(response: ___R) -> Self::Output {
876 ::core::result::Result::Err(response)
877 }
878 }
879
880 pub struct UnlockBus;
881
882 impl ::fidl_next::Method for UnlockBus {
883 const ORDINAL: u64 = 3150764477565251378;
884 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
885 ::fidl_next::protocol::Flexibility::Strict;
886
887 type Protocol = crate::SpiImpl;
888
889 type Request = crate::wire::SpiImplUnlockBusRequest;
890 }
891
892 impl ::fidl_next::TwoWayMethod for UnlockBus {
893 type Response = ::fidl_next::wire::Result<
894 'static,
895 crate::wire::SpiImplUnlockBusResponse,
896 ::fidl_next::wire::fuchsia::Status,
897 >;
898 }
899
900 impl<___R> ::fidl_next::Respond<___R> for UnlockBus {
901 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
902
903 fn respond(response: ___R) -> Self::Output {
904 ::core::result::Result::Ok(response)
905 }
906 }
907
908 impl<___R> ::fidl_next::RespondErr<___R> for UnlockBus {
909 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
910
911 fn respond_err(response: ___R) -> Self::Output {
912 ::core::result::Result::Err(response)
913 }
914 }
915
916 pub struct RegisterVmo;
917
918 impl ::fidl_next::Method for RegisterVmo {
919 const ORDINAL: u64 = 2270783649342134233;
920 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
921 ::fidl_next::protocol::Flexibility::Strict;
922
923 type Protocol = crate::SpiImpl;
924
925 type Request = crate::wire::SpiImplRegisterVmoRequest;
926 }
927
928 impl ::fidl_next::TwoWayMethod for RegisterVmo {
929 type Response = ::fidl_next::wire::Result<
930 'static,
931 crate::wire::SpiImplRegisterVmoResponse,
932 ::fidl_next::wire::fuchsia::Status,
933 >;
934 }
935
936 impl<___R> ::fidl_next::Respond<___R> for RegisterVmo {
937 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
938
939 fn respond(response: ___R) -> Self::Output {
940 ::core::result::Result::Ok(response)
941 }
942 }
943
944 impl<___R> ::fidl_next::RespondErr<___R> for RegisterVmo {
945 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
946
947 fn respond_err(response: ___R) -> Self::Output {
948 ::core::result::Result::Err(response)
949 }
950 }
951
952 pub struct UnregisterVmo;
953
954 impl ::fidl_next::Method for UnregisterVmo {
955 const ORDINAL: u64 = 8778583385931240091;
956 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
957 ::fidl_next::protocol::Flexibility::Strict;
958
959 type Protocol = crate::SpiImpl;
960
961 type Request = crate::wire::SpiImplUnregisterVmoRequest;
962 }
963
964 impl ::fidl_next::TwoWayMethod for UnregisterVmo {
965 type Response = ::fidl_next::wire::Result<
966 'static,
967 crate::wire::SpiImplUnregisterVmoResponse,
968 ::fidl_next::wire::fuchsia::Status,
969 >;
970 }
971
972 impl<___R> ::fidl_next::Respond<___R> for UnregisterVmo {
973 type Output = ::core::result::Result<
974 crate::generic::SpiImplUnregisterVmoResponse<___R>,
975 ::fidl_next::never::Never,
976 >;
977
978 fn respond(response: ___R) -> Self::Output {
979 ::core::result::Result::Ok(crate::generic::SpiImplUnregisterVmoResponse {
980 vmo: response,
981 })
982 }
983 }
984
985 impl<___R> ::fidl_next::RespondErr<___R> for UnregisterVmo {
986 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
987
988 fn respond_err(response: ___R) -> Self::Output {
989 ::core::result::Result::Err(response)
990 }
991 }
992
993 pub struct ReleaseRegisteredVmos;
994
995 impl ::fidl_next::Method for ReleaseRegisteredVmos {
996 const ORDINAL: u64 = 5302547493468731494;
997 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
998 ::fidl_next::protocol::Flexibility::Strict;
999
1000 type Protocol = crate::SpiImpl;
1001
1002 type Request = crate::wire::SpiImplReleaseRegisteredVmosRequest;
1003 }
1004
1005 pub struct TransmitVmo;
1006
1007 impl ::fidl_next::Method for TransmitVmo {
1008 const ORDINAL: u64 = 1490935665662854691;
1009 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
1010 ::fidl_next::protocol::Flexibility::Strict;
1011
1012 type Protocol = crate::SpiImpl;
1013
1014 type Request = crate::wire::SpiImplTransmitVmoRequest;
1015 }
1016
1017 impl ::fidl_next::TwoWayMethod for TransmitVmo {
1018 type Response = ::fidl_next::wire::Result<
1019 'static,
1020 crate::wire::SpiImplTransmitVmoResponse,
1021 ::fidl_next::wire::fuchsia::Status,
1022 >;
1023 }
1024
1025 impl<___R> ::fidl_next::Respond<___R> for TransmitVmo {
1026 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
1027
1028 fn respond(response: ___R) -> Self::Output {
1029 ::core::result::Result::Ok(response)
1030 }
1031 }
1032
1033 impl<___R> ::fidl_next::RespondErr<___R> for TransmitVmo {
1034 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
1035
1036 fn respond_err(response: ___R) -> Self::Output {
1037 ::core::result::Result::Err(response)
1038 }
1039 }
1040
1041 pub struct ReceiveVmo;
1042
1043 impl ::fidl_next::Method for ReceiveVmo {
1044 const ORDINAL: u64 = 7091744647492940488;
1045 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
1046 ::fidl_next::protocol::Flexibility::Strict;
1047
1048 type Protocol = crate::SpiImpl;
1049
1050 type Request = crate::wire::SpiImplReceiveVmoRequest;
1051 }
1052
1053 impl ::fidl_next::TwoWayMethod for ReceiveVmo {
1054 type Response = ::fidl_next::wire::Result<
1055 'static,
1056 crate::wire::SpiImplReceiveVmoResponse,
1057 ::fidl_next::wire::fuchsia::Status,
1058 >;
1059 }
1060
1061 impl<___R> ::fidl_next::Respond<___R> for ReceiveVmo {
1062 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
1063
1064 fn respond(response: ___R) -> Self::Output {
1065 ::core::result::Result::Ok(response)
1066 }
1067 }
1068
1069 impl<___R> ::fidl_next::RespondErr<___R> for ReceiveVmo {
1070 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
1071
1072 fn respond_err(response: ___R) -> Self::Output {
1073 ::core::result::Result::Err(response)
1074 }
1075 }
1076
1077 pub struct ExchangeVmo;
1078
1079 impl ::fidl_next::Method for ExchangeVmo {
1080 const ORDINAL: u64 = 3592177641282126076;
1081 const FLEXIBILITY: ::fidl_next::protocol::Flexibility =
1082 ::fidl_next::protocol::Flexibility::Strict;
1083
1084 type Protocol = crate::SpiImpl;
1085
1086 type Request = crate::wire::SpiImplExchangeVmoRequest;
1087 }
1088
1089 impl ::fidl_next::TwoWayMethod for ExchangeVmo {
1090 type Response = ::fidl_next::wire::Result<
1091 'static,
1092 crate::wire::SpiImplExchangeVmoResponse,
1093 ::fidl_next::wire::fuchsia::Status,
1094 >;
1095 }
1096
1097 impl<___R> ::fidl_next::Respond<___R> for ExchangeVmo {
1098 type Output = ::core::result::Result<___R, ::fidl_next::never::Never>;
1099
1100 fn respond(response: ___R) -> Self::Output {
1101 ::core::result::Result::Ok(response)
1102 }
1103 }
1104
1105 impl<___R> ::fidl_next::RespondErr<___R> for ExchangeVmo {
1106 type Output = ::core::result::Result<::fidl_next::never::Never, ___R>;
1107
1108 fn respond_err(response: ___R) -> Self::Output {
1109 ::core::result::Result::Err(response)
1110 }
1111 }
1112
1113 mod ___detail {
1114 unsafe impl<___T> ::fidl_next::HasConnectionHandles<___T> for crate::SpiImpl
1115 where
1116 ___T: ::fidl_next::Transport,
1117 {
1118 type Client = SpiImplClient<___T>;
1119 type Server = SpiImplServer<___T>;
1120 }
1121
1122 #[repr(transparent)]
1124 pub struct SpiImplClient<___T: ::fidl_next::Transport> {
1125 #[allow(dead_code)]
1126 client: ::fidl_next::protocol::Client<___T>,
1127 }
1128
1129 impl<___T> SpiImplClient<___T>
1130 where
1131 ___T: ::fidl_next::Transport,
1132 {
1133 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
1134 pub fn get_chip_select_count(
1135 &self,
1136 ) -> ::fidl_next::TwoWayFuture<'_, super::GetChipSelectCount, ___T> {
1137 ::fidl_next::TwoWayFuture::from_untyped(
1138 self.client.send_two_way::<::fidl_next::wire::EmptyMessageBody>(
1139 4261972386852856527,
1140 <super::GetChipSelectCount as ::fidl_next::Method>::FLEXIBILITY,
1141 (),
1142 ),
1143 )
1144 }
1145
1146 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1147 pub fn transmit_vector(
1148 &self,
1149
1150 chip_select: impl ::fidl_next::Encode<
1151 ::fidl_next::wire::Uint32,
1152 <___T as ::fidl_next::Transport>::SendBuffer,
1153 >,
1154
1155 data: impl ::fidl_next::Encode<
1156 ::fidl_next::wire::Vector<'static, u8>,
1157 <___T as ::fidl_next::Transport>::SendBuffer,
1158 >,
1159 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVector, ___T>
1160 where
1161 <___T as ::fidl_next::Transport>::SendBuffer:
1162 ::fidl_next::encoder::InternalHandleEncoder,
1163 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::Encoder,
1164 {
1165 self.transmit_vector_with(crate::generic::SpiImplTransmitVectorRequest {
1166 chip_select,
1167
1168 data,
1169 })
1170 }
1171
1172 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1173 pub fn transmit_vector_with<___R>(
1174 &self,
1175 request: ___R,
1176 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVector, ___T>
1177 where
1178 ___R: ::fidl_next::Encode<
1179 crate::wire::SpiImplTransmitVectorRequest<'static>,
1180 <___T as ::fidl_next::Transport>::SendBuffer,
1181 >,
1182 {
1183 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1184 7287789131276374998,
1185 <super::TransmitVector as ::fidl_next::Method>::FLEXIBILITY,
1186 request,
1187 ))
1188 }
1189
1190 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1191 pub fn receive_vector(
1192 &self,
1193
1194 chip_select: impl ::fidl_next::Encode<
1195 ::fidl_next::wire::Uint32,
1196 <___T as ::fidl_next::Transport>::SendBuffer,
1197 >,
1198
1199 size: impl ::fidl_next::Encode<
1200 ::fidl_next::wire::Uint32,
1201 <___T as ::fidl_next::Transport>::SendBuffer,
1202 >,
1203 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVector, ___T>
1204 where
1205 <___T as ::fidl_next::Transport>::SendBuffer:
1206 ::fidl_next::encoder::InternalHandleEncoder,
1207 {
1208 self.receive_vector_with(crate::generic::SpiImplReceiveVectorRequest {
1209 chip_select,
1210
1211 size,
1212 })
1213 }
1214
1215 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1216 pub fn receive_vector_with<___R>(
1217 &self,
1218 request: ___R,
1219 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVector, ___T>
1220 where
1221 ___R: ::fidl_next::Encode<
1222 crate::wire::SpiImplReceiveVectorRequest,
1223 <___T as ::fidl_next::Transport>::SendBuffer,
1224 >,
1225 {
1226 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1227 4813495552606122700,
1228 <super::ReceiveVector as ::fidl_next::Method>::FLEXIBILITY,
1229 request,
1230 ))
1231 }
1232
1233 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1234 pub fn exchange_vector(
1235 &self,
1236
1237 chip_select: impl ::fidl_next::Encode<
1238 ::fidl_next::wire::Uint32,
1239 <___T as ::fidl_next::Transport>::SendBuffer,
1240 >,
1241
1242 txdata: impl ::fidl_next::Encode<
1243 ::fidl_next::wire::Vector<'static, u8>,
1244 <___T as ::fidl_next::Transport>::SendBuffer,
1245 >,
1246 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVector, ___T>
1247 where
1248 <___T as ::fidl_next::Transport>::SendBuffer:
1249 ::fidl_next::encoder::InternalHandleEncoder,
1250 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::Encoder,
1251 {
1252 self.exchange_vector_with(crate::generic::SpiImplExchangeVectorRequest {
1253 chip_select,
1254
1255 txdata,
1256 })
1257 }
1258
1259 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1260 pub fn exchange_vector_with<___R>(
1261 &self,
1262 request: ___R,
1263 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVector, ___T>
1264 where
1265 ___R: ::fidl_next::Encode<
1266 crate::wire::SpiImplExchangeVectorRequest<'static>,
1267 <___T as ::fidl_next::Transport>::SendBuffer,
1268 >,
1269 {
1270 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1271 3844617764012354164,
1272 <super::ExchangeVector as ::fidl_next::Method>::FLEXIBILITY,
1273 request,
1274 ))
1275 }
1276
1277 #[doc = " Lock the bus.\n"]
1278 pub fn lock_bus(
1279 &self,
1280
1281 chip_select: impl ::fidl_next::Encode<
1282 ::fidl_next::wire::Uint32,
1283 <___T as ::fidl_next::Transport>::SendBuffer,
1284 >,
1285 ) -> ::fidl_next::TwoWayFuture<'_, super::LockBus, ___T>
1286 where
1287 <___T as ::fidl_next::Transport>::SendBuffer:
1288 ::fidl_next::encoder::InternalHandleEncoder,
1289 {
1290 self.lock_bus_with(crate::generic::SpiImplLockBusRequest { chip_select })
1291 }
1292
1293 #[doc = " Lock the bus.\n"]
1294 pub fn lock_bus_with<___R>(
1295 &self,
1296 request: ___R,
1297 ) -> ::fidl_next::TwoWayFuture<'_, super::LockBus, ___T>
1298 where
1299 ___R: ::fidl_next::Encode<
1300 crate::wire::SpiImplLockBusRequest,
1301 <___T as ::fidl_next::Transport>::SendBuffer,
1302 >,
1303 {
1304 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1305 9187537331803160557,
1306 <super::LockBus as ::fidl_next::Method>::FLEXIBILITY,
1307 request,
1308 ))
1309 }
1310
1311 #[doc = " Unlock the bus.\n"]
1312 pub fn unlock_bus(
1313 &self,
1314
1315 chip_select: impl ::fidl_next::Encode<
1316 ::fidl_next::wire::Uint32,
1317 <___T as ::fidl_next::Transport>::SendBuffer,
1318 >,
1319 ) -> ::fidl_next::TwoWayFuture<'_, super::UnlockBus, ___T>
1320 where
1321 <___T as ::fidl_next::Transport>::SendBuffer:
1322 ::fidl_next::encoder::InternalHandleEncoder,
1323 {
1324 self.unlock_bus_with(crate::generic::SpiImplUnlockBusRequest { chip_select })
1325 }
1326
1327 #[doc = " Unlock the bus.\n"]
1328 pub fn unlock_bus_with<___R>(
1329 &self,
1330 request: ___R,
1331 ) -> ::fidl_next::TwoWayFuture<'_, super::UnlockBus, ___T>
1332 where
1333 ___R: ::fidl_next::Encode<
1334 crate::wire::SpiImplUnlockBusRequest,
1335 <___T as ::fidl_next::Transport>::SendBuffer,
1336 >,
1337 {
1338 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1339 3150764477565251378,
1340 <super::UnlockBus as ::fidl_next::Method>::FLEXIBILITY,
1341 request,
1342 ))
1343 }
1344
1345 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1346 pub fn register_vmo(
1347 &self,
1348
1349 chip_select: impl ::fidl_next::Encode<
1350 ::fidl_next::wire::Uint32,
1351 <___T as ::fidl_next::Transport>::SendBuffer,
1352 >,
1353
1354 vmo_id: impl ::fidl_next::Encode<
1355 ::fidl_next::wire::Uint32,
1356 <___T as ::fidl_next::Transport>::SendBuffer,
1357 >,
1358
1359 vmo: impl ::fidl_next::Encode<
1360 ::fidl_next_fuchsia_mem::wire::Range,
1361 <___T as ::fidl_next::Transport>::SendBuffer,
1362 >,
1363
1364 rights: impl ::fidl_next::Encode<
1365 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoRight,
1366 <___T as ::fidl_next::Transport>::SendBuffer,
1367 >,
1368 ) -> ::fidl_next::TwoWayFuture<'_, super::RegisterVmo, ___T>
1369 where
1370 <___T as ::fidl_next::Transport>::SendBuffer:
1371 ::fidl_next::encoder::InternalHandleEncoder,
1372 <___T as ::fidl_next::Transport>::SendBuffer: ::fidl_next::fuchsia::HandleEncoder,
1373 {
1374 self.register_vmo_with(crate::generic::SpiImplRegisterVmoRequest {
1375 chip_select,
1376
1377 vmo_id,
1378
1379 vmo,
1380
1381 rights,
1382 })
1383 }
1384
1385 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1386 pub fn register_vmo_with<___R>(
1387 &self,
1388 request: ___R,
1389 ) -> ::fidl_next::TwoWayFuture<'_, super::RegisterVmo, ___T>
1390 where
1391 ___R: ::fidl_next::Encode<
1392 crate::wire::SpiImplRegisterVmoRequest,
1393 <___T as ::fidl_next::Transport>::SendBuffer,
1394 >,
1395 {
1396 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1397 2270783649342134233,
1398 <super::RegisterVmo as ::fidl_next::Method>::FLEXIBILITY,
1399 request,
1400 ))
1401 }
1402
1403 pub fn unregister_vmo(
1404 &self,
1405
1406 chip_select: impl ::fidl_next::Encode<
1407 ::fidl_next::wire::Uint32,
1408 <___T as ::fidl_next::Transport>::SendBuffer,
1409 >,
1410
1411 vmo_id: impl ::fidl_next::Encode<
1412 ::fidl_next::wire::Uint32,
1413 <___T as ::fidl_next::Transport>::SendBuffer,
1414 >,
1415 ) -> ::fidl_next::TwoWayFuture<'_, super::UnregisterVmo, ___T>
1416 where
1417 <___T as ::fidl_next::Transport>::SendBuffer:
1418 ::fidl_next::encoder::InternalHandleEncoder,
1419 {
1420 self.unregister_vmo_with(crate::generic::SpiImplUnregisterVmoRequest {
1421 chip_select,
1422
1423 vmo_id,
1424 })
1425 }
1426
1427 pub fn unregister_vmo_with<___R>(
1428 &self,
1429 request: ___R,
1430 ) -> ::fidl_next::TwoWayFuture<'_, super::UnregisterVmo, ___T>
1431 where
1432 ___R: ::fidl_next::Encode<
1433 crate::wire::SpiImplUnregisterVmoRequest,
1434 <___T as ::fidl_next::Transport>::SendBuffer,
1435 >,
1436 {
1437 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1438 8778583385931240091,
1439 <super::UnregisterVmo as ::fidl_next::Method>::FLEXIBILITY,
1440 request,
1441 ))
1442 }
1443
1444 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1445 pub fn release_registered_vmos(
1446 &self,
1447
1448 chip_select: impl ::fidl_next::Encode<
1449 ::fidl_next::wire::Uint32,
1450 <___T as ::fidl_next::Transport>::SendBuffer,
1451 >,
1452 ) -> ::fidl_next::SendFuture<'_, ___T>
1453 where
1454 <___T as ::fidl_next::Transport>::SendBuffer:
1455 ::fidl_next::encoder::InternalHandleEncoder,
1456 {
1457 self.release_registered_vmos_with(
1458 crate::generic::SpiImplReleaseRegisteredVmosRequest { chip_select },
1459 )
1460 }
1461
1462 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1463 pub fn release_registered_vmos_with<___R>(
1464 &self,
1465 request: ___R,
1466 ) -> ::fidl_next::SendFuture<'_, ___T>
1467 where
1468 ___R: ::fidl_next::Encode<
1469 crate::wire::SpiImplReleaseRegisteredVmosRequest,
1470 <___T as ::fidl_next::Transport>::SendBuffer,
1471 >,
1472 {
1473 ::fidl_next::SendFuture::from_untyped(self.client.send_one_way(
1474 5302547493468731494,
1475 <super::ReleaseRegisteredVmos as ::fidl_next::Method>::FLEXIBILITY,
1476 request,
1477 ))
1478 }
1479
1480 pub fn transmit_vmo(
1481 &self,
1482
1483 chip_select: impl ::fidl_next::Encode<
1484 ::fidl_next::wire::Uint32,
1485 <___T as ::fidl_next::Transport>::SendBuffer,
1486 >,
1487
1488 buffer: impl ::fidl_next::Encode<
1489 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1490 <___T as ::fidl_next::Transport>::SendBuffer,
1491 >,
1492 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVmo, ___T>
1493 where
1494 <___T as ::fidl_next::Transport>::SendBuffer:
1495 ::fidl_next::encoder::InternalHandleEncoder,
1496 {
1497 self.transmit_vmo_with(crate::generic::SpiImplTransmitVmoRequest {
1498 chip_select,
1499
1500 buffer,
1501 })
1502 }
1503
1504 pub fn transmit_vmo_with<___R>(
1505 &self,
1506 request: ___R,
1507 ) -> ::fidl_next::TwoWayFuture<'_, super::TransmitVmo, ___T>
1508 where
1509 ___R: ::fidl_next::Encode<
1510 crate::wire::SpiImplTransmitVmoRequest,
1511 <___T as ::fidl_next::Transport>::SendBuffer,
1512 >,
1513 {
1514 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1515 1490935665662854691,
1516 <super::TransmitVmo as ::fidl_next::Method>::FLEXIBILITY,
1517 request,
1518 ))
1519 }
1520
1521 pub fn receive_vmo(
1522 &self,
1523
1524 chip_select: impl ::fidl_next::Encode<
1525 ::fidl_next::wire::Uint32,
1526 <___T as ::fidl_next::Transport>::SendBuffer,
1527 >,
1528
1529 buffer: impl ::fidl_next::Encode<
1530 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1531 <___T as ::fidl_next::Transport>::SendBuffer,
1532 >,
1533 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVmo, ___T>
1534 where
1535 <___T as ::fidl_next::Transport>::SendBuffer:
1536 ::fidl_next::encoder::InternalHandleEncoder,
1537 {
1538 self.receive_vmo_with(crate::generic::SpiImplReceiveVmoRequest {
1539 chip_select,
1540
1541 buffer,
1542 })
1543 }
1544
1545 pub fn receive_vmo_with<___R>(
1546 &self,
1547 request: ___R,
1548 ) -> ::fidl_next::TwoWayFuture<'_, super::ReceiveVmo, ___T>
1549 where
1550 ___R: ::fidl_next::Encode<
1551 crate::wire::SpiImplReceiveVmoRequest,
1552 <___T as ::fidl_next::Transport>::SendBuffer,
1553 >,
1554 {
1555 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1556 7091744647492940488,
1557 <super::ReceiveVmo as ::fidl_next::Method>::FLEXIBILITY,
1558 request,
1559 ))
1560 }
1561
1562 pub fn exchange_vmo(
1563 &self,
1564
1565 chip_select: impl ::fidl_next::Encode<
1566 ::fidl_next::wire::Uint32,
1567 <___T as ::fidl_next::Transport>::SendBuffer,
1568 >,
1569
1570 tx_buffer: impl ::fidl_next::Encode<
1571 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1572 <___T as ::fidl_next::Transport>::SendBuffer,
1573 >,
1574
1575 rx_buffer: impl ::fidl_next::Encode<
1576 ::fidl_next_fuchsia_hardware_sharedmemory::wire::SharedVmoBuffer,
1577 <___T as ::fidl_next::Transport>::SendBuffer,
1578 >,
1579 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVmo, ___T>
1580 where
1581 <___T as ::fidl_next::Transport>::SendBuffer:
1582 ::fidl_next::encoder::InternalHandleEncoder,
1583 {
1584 self.exchange_vmo_with(crate::generic::SpiImplExchangeVmoRequest {
1585 chip_select,
1586
1587 tx_buffer,
1588
1589 rx_buffer,
1590 })
1591 }
1592
1593 pub fn exchange_vmo_with<___R>(
1594 &self,
1595 request: ___R,
1596 ) -> ::fidl_next::TwoWayFuture<'_, super::ExchangeVmo, ___T>
1597 where
1598 ___R: ::fidl_next::Encode<
1599 crate::wire::SpiImplExchangeVmoRequest,
1600 <___T as ::fidl_next::Transport>::SendBuffer,
1601 >,
1602 {
1603 ::fidl_next::TwoWayFuture::from_untyped(self.client.send_two_way(
1604 3592177641282126076,
1605 <super::ExchangeVmo as ::fidl_next::Method>::FLEXIBILITY,
1606 request,
1607 ))
1608 }
1609 }
1610
1611 #[repr(transparent)]
1613 pub struct SpiImplServer<___T: ::fidl_next::Transport> {
1614 server: ::fidl_next::protocol::Server<___T>,
1615 }
1616
1617 impl<___T> SpiImplServer<___T> where ___T: ::fidl_next::Transport {}
1618 }
1619}
1620
1621#[diagnostic::on_unimplemented(
1622 note = "If {Self} implements the non-local SpiImplClientHandler trait, use `spawn_as_local` or the `Local` adapter type"
1623)]
1624
1625pub trait SpiImplLocalClientHandler<
1629 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1630 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1631>
1632{
1633}
1634
1635impl<___H, ___T> ::fidl_next::DispatchLocalClientMessage<___H, ___T> for SpiImpl
1636where
1637 ___H: SpiImplLocalClientHandler<___T>,
1638 ___T: ::fidl_next::Transport,
1639{
1640 async fn on_event(
1641 handler: &mut ___H,
1642 mut message: ::fidl_next::Message<___T>,
1643 ) -> ::core::result::Result<(), ::fidl_next::ProtocolError<___T::Error>> {
1644 match *message.header().ordinal {
1645 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1646 }
1647 }
1648}
1649
1650#[diagnostic::on_unimplemented(
1651 note = "If {Self} implements the non-local SpiImplServerHandler trait, use `spawn_as_local` or the `Local` adapter type"
1652)]
1653
1654pub trait SpiImplLocalServerHandler<
1658 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
1659 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
1660>
1661{
1662 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
1663 fn get_chip_select_count(
1664 &mut self,
1665
1666 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
1667 ) -> impl ::core::future::Future<Output = ()>;
1668
1669 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
1670 fn transmit_vector(
1671 &mut self,
1672
1673 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
1674
1675 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
1676 ) -> impl ::core::future::Future<Output = ()>;
1677
1678 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
1679 fn receive_vector(
1680 &mut self,
1681
1682 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
1683
1684 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
1685 ) -> impl ::core::future::Future<Output = ()>;
1686
1687 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
1688 fn exchange_vector(
1689 &mut self,
1690
1691 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
1692
1693 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
1694 ) -> impl ::core::future::Future<Output = ()>;
1695
1696 #[doc = " Lock the bus.\n"]
1697 fn lock_bus(
1698 &mut self,
1699
1700 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
1701
1702 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
1703 ) -> impl ::core::future::Future<Output = ()>;
1704
1705 #[doc = " Unlock the bus.\n"]
1706 fn unlock_bus(
1707 &mut self,
1708
1709 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
1710
1711 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
1712 ) -> impl ::core::future::Future<Output = ()>;
1713
1714 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
1715 fn register_vmo(
1716 &mut self,
1717
1718 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
1719
1720 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
1721 ) -> impl ::core::future::Future<Output = ()>;
1722
1723 fn unregister_vmo(
1724 &mut self,
1725
1726 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
1727
1728 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
1729 ) -> impl ::core::future::Future<Output = ()>;
1730
1731 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
1732 fn release_registered_vmos(
1733 &mut self,
1734
1735 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
1736 ) -> impl ::core::future::Future<Output = ()>;
1737
1738 fn transmit_vmo(
1739 &mut self,
1740
1741 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
1742
1743 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
1744 ) -> impl ::core::future::Future<Output = ()>;
1745
1746 fn receive_vmo(
1747 &mut self,
1748
1749 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
1750
1751 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
1752 ) -> impl ::core::future::Future<Output = ()>;
1753
1754 fn exchange_vmo(
1755 &mut self,
1756
1757 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
1758
1759 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
1760 ) -> impl ::core::future::Future<Output = ()>;
1761}
1762
1763impl<___H, ___T> ::fidl_next::DispatchLocalServerMessage<___H, ___T> for SpiImpl
1764where
1765 ___H: SpiImplLocalServerHandler<___T>,
1766 ___T: ::fidl_next::Transport,
1767 for<'de> crate::wire::SpiImplTransmitVectorRequest<'de>: ::fidl_next::Decode<
1768 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1769 Constraint = (),
1770 >,
1771 for<'de> crate::wire::SpiImplReceiveVectorRequest: ::fidl_next::Decode<
1772 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1773 Constraint = (),
1774 >,
1775 for<'de> crate::wire::SpiImplExchangeVectorRequest<'de>: ::fidl_next::Decode<
1776 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1777 Constraint = (),
1778 >,
1779 for<'de> crate::wire::SpiImplLockBusRequest: ::fidl_next::Decode<
1780 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1781 Constraint = (),
1782 >,
1783 for<'de> crate::wire::SpiImplUnlockBusRequest: ::fidl_next::Decode<
1784 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1785 Constraint = (),
1786 >,
1787 for<'de> crate::wire::SpiImplRegisterVmoRequest: ::fidl_next::Decode<
1788 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1789 Constraint = (),
1790 >,
1791 for<'de> crate::wire::SpiImplUnregisterVmoRequest: ::fidl_next::Decode<
1792 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1793 Constraint = (),
1794 >,
1795 for<'de> crate::wire::SpiImplReleaseRegisteredVmosRequest: ::fidl_next::Decode<
1796 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1797 Constraint = (),
1798 >,
1799 for<'de> crate::wire::SpiImplTransmitVmoRequest: ::fidl_next::Decode<
1800 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1801 Constraint = (),
1802 >,
1803 for<'de> crate::wire::SpiImplReceiveVmoRequest: ::fidl_next::Decode<
1804 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1805 Constraint = (),
1806 >,
1807 for<'de> crate::wire::SpiImplExchangeVmoRequest: ::fidl_next::Decode<
1808 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
1809 Constraint = (),
1810 >,
1811{
1812 async fn on_one_way(
1813 handler: &mut ___H,
1814 mut message: ::fidl_next::Message<___T>,
1815 ) -> ::core::result::Result<
1816 (),
1817 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
1818 > {
1819 match *message.header().ordinal {
1820 5302547493468731494 => match ::fidl_next::AsDecoderExt::into_decoded(message) {
1821 Ok(decoded) => {
1822 handler
1823 .release_registered_vmos(::fidl_next::Request::from_decoded(decoded))
1824 .await;
1825 Ok(())
1826 }
1827 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1828 ordinal: 5302547493468731494,
1829 error,
1830 }),
1831 },
1832
1833 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
1834 }
1835 }
1836
1837 async fn on_two_way(
1838 handler: &mut ___H,
1839 mut message: ::fidl_next::Message<___T>,
1840 responder: ::fidl_next::protocol::Responder<___T>,
1841 ) -> ::core::result::Result<
1842 (),
1843 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
1844 > {
1845 match *message.header().ordinal {
1846 4261972386852856527 => {
1847 let responder = ::fidl_next::Responder::from_untyped(responder);
1848
1849 handler.get_chip_select_count(responder).await;
1850 Ok(())
1851 }
1852
1853 7287789131276374998 => {
1854 let responder = ::fidl_next::Responder::from_untyped(responder);
1855
1856 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1857 Ok(decoded) => {
1858 handler
1859 .transmit_vector(::fidl_next::Request::from_decoded(decoded), responder)
1860 .await;
1861 Ok(())
1862 }
1863 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1864 ordinal: 7287789131276374998,
1865 error,
1866 }),
1867 }
1868 }
1869
1870 4813495552606122700 => {
1871 let responder = ::fidl_next::Responder::from_untyped(responder);
1872
1873 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1874 Ok(decoded) => {
1875 handler
1876 .receive_vector(::fidl_next::Request::from_decoded(decoded), responder)
1877 .await;
1878 Ok(())
1879 }
1880 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1881 ordinal: 4813495552606122700,
1882 error,
1883 }),
1884 }
1885 }
1886
1887 3844617764012354164 => {
1888 let responder = ::fidl_next::Responder::from_untyped(responder);
1889
1890 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1891 Ok(decoded) => {
1892 handler
1893 .exchange_vector(::fidl_next::Request::from_decoded(decoded), responder)
1894 .await;
1895 Ok(())
1896 }
1897 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1898 ordinal: 3844617764012354164,
1899 error,
1900 }),
1901 }
1902 }
1903
1904 9187537331803160557 => {
1905 let responder = ::fidl_next::Responder::from_untyped(responder);
1906
1907 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1908 Ok(decoded) => {
1909 handler
1910 .lock_bus(::fidl_next::Request::from_decoded(decoded), responder)
1911 .await;
1912 Ok(())
1913 }
1914 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1915 ordinal: 9187537331803160557,
1916 error,
1917 }),
1918 }
1919 }
1920
1921 3150764477565251378 => {
1922 let responder = ::fidl_next::Responder::from_untyped(responder);
1923
1924 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1925 Ok(decoded) => {
1926 handler
1927 .unlock_bus(::fidl_next::Request::from_decoded(decoded), responder)
1928 .await;
1929 Ok(())
1930 }
1931 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1932 ordinal: 3150764477565251378,
1933 error,
1934 }),
1935 }
1936 }
1937
1938 2270783649342134233 => {
1939 let responder = ::fidl_next::Responder::from_untyped(responder);
1940
1941 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1942 Ok(decoded) => {
1943 handler
1944 .register_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1945 .await;
1946 Ok(())
1947 }
1948 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1949 ordinal: 2270783649342134233,
1950 error,
1951 }),
1952 }
1953 }
1954
1955 8778583385931240091 => {
1956 let responder = ::fidl_next::Responder::from_untyped(responder);
1957
1958 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1959 Ok(decoded) => {
1960 handler
1961 .unregister_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1962 .await;
1963 Ok(())
1964 }
1965 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1966 ordinal: 8778583385931240091,
1967 error,
1968 }),
1969 }
1970 }
1971
1972 1490935665662854691 => {
1973 let responder = ::fidl_next::Responder::from_untyped(responder);
1974
1975 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1976 Ok(decoded) => {
1977 handler
1978 .transmit_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1979 .await;
1980 Ok(())
1981 }
1982 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
1983 ordinal: 1490935665662854691,
1984 error,
1985 }),
1986 }
1987 }
1988
1989 7091744647492940488 => {
1990 let responder = ::fidl_next::Responder::from_untyped(responder);
1991
1992 match ::fidl_next::AsDecoderExt::into_decoded(message) {
1993 Ok(decoded) => {
1994 handler
1995 .receive_vmo(::fidl_next::Request::from_decoded(decoded), responder)
1996 .await;
1997 Ok(())
1998 }
1999 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2000 ordinal: 7091744647492940488,
2001 error,
2002 }),
2003 }
2004 }
2005
2006 3592177641282126076 => {
2007 let responder = ::fidl_next::Responder::from_untyped(responder);
2008
2009 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2010 Ok(decoded) => {
2011 handler
2012 .exchange_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2013 .await;
2014 Ok(())
2015 }
2016 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2017 ordinal: 3592177641282126076,
2018 error,
2019 }),
2020 }
2021 }
2022
2023 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2024 }
2025 }
2026}
2027
2028pub trait SpiImplClientHandler<
2032 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
2033 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
2034>
2035{
2036}
2037
2038impl<___H, ___T> ::fidl_next::DispatchClientMessage<___H, ___T> for SpiImpl
2039where
2040 ___H: SpiImplClientHandler<___T> + ::core::marker::Send,
2041 ___T: ::fidl_next::Transport,
2042{
2043 async fn on_event(
2044 handler: &mut ___H,
2045 mut message: ::fidl_next::Message<___T>,
2046 ) -> ::core::result::Result<(), ::fidl_next::ProtocolError<___T::Error>> {
2047 match *message.header().ordinal {
2048 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2049 }
2050 }
2051}
2052
2053pub trait SpiImplServerHandler<
2057 #[cfg(feature = "driver")] ___T: ::fidl_next::Transport = ::fdf_fidl::DriverChannel,
2058 #[cfg(not(feature = "driver"))] ___T: ::fidl_next::Transport,
2059>
2060{
2061 #[doc = " Returns the number of chip select lines available or provided by the driver instance.\n To be used as a limit on the acceptable values for the `chip_select\' field in the Exchange()\n and ExchangeVmo() methods.\n"]
2062 fn get_chip_select_count(
2063 &mut self,
2064
2065 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
2066 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2067
2068 #[doc = " Half-duplex transmit data to a SPI device; always transmits the entire buffer on success.\n"]
2069 fn transmit_vector(
2070 &mut self,
2071
2072 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
2073
2074 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
2075 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2076
2077 #[doc = " Half-duplex receive data from a SPI device; always reads the full size requested.\n"]
2078 fn receive_vector(
2079 &mut self,
2080
2081 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
2082
2083 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
2084 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2085
2086 #[doc = " Full-duplex SPI transaction. Received data will exactly equal the length of the transmit\n buffer.\n"]
2087 fn exchange_vector(
2088 &mut self,
2089
2090 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
2091
2092 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
2093 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2094
2095 #[doc = " Lock the bus.\n"]
2096 fn lock_bus(
2097 &mut self,
2098
2099 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
2100
2101 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
2102 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2103
2104 #[doc = " Unlock the bus.\n"]
2105 fn unlock_bus(
2106 &mut self,
2107
2108 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
2109
2110 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
2111 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2112
2113 #[doc = " rights is a bit field containing SpiVmoRight values, and determines the read/write\n permissions used by the implementation when pinning or mapping the VMO.\n"]
2114 fn register_vmo(
2115 &mut self,
2116
2117 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
2118
2119 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
2120 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2121
2122 fn unregister_vmo(
2123 &mut self,
2124
2125 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
2126
2127 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
2128 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2129
2130 #[doc = " Release all VMOs registered to this chip_select. Called by the core driver after the client\n has disconnected and the VMOs are no longer needed.\n"]
2131 fn release_registered_vmos(
2132 &mut self,
2133
2134 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
2135 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2136
2137 fn transmit_vmo(
2138 &mut self,
2139
2140 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
2141
2142 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
2143 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2144
2145 fn receive_vmo(
2146 &mut self,
2147
2148 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
2149
2150 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
2151 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2152
2153 fn exchange_vmo(
2154 &mut self,
2155
2156 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
2157
2158 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
2159 ) -> impl ::core::future::Future<Output = ()> + ::core::marker::Send;
2160}
2161
2162impl<___H, ___T> ::fidl_next::DispatchServerMessage<___H, ___T> for SpiImpl
2163where
2164 ___H: SpiImplServerHandler<___T> + ::core::marker::Send,
2165 ___T: ::fidl_next::Transport,
2166 for<'de> crate::wire::SpiImplTransmitVectorRequest<'de>: ::fidl_next::Decode<
2167 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2168 Constraint = (),
2169 >,
2170 for<'de> crate::wire::SpiImplReceiveVectorRequest: ::fidl_next::Decode<
2171 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2172 Constraint = (),
2173 >,
2174 for<'de> crate::wire::SpiImplExchangeVectorRequest<'de>: ::fidl_next::Decode<
2175 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2176 Constraint = (),
2177 >,
2178 for<'de> crate::wire::SpiImplLockBusRequest: ::fidl_next::Decode<
2179 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2180 Constraint = (),
2181 >,
2182 for<'de> crate::wire::SpiImplUnlockBusRequest: ::fidl_next::Decode<
2183 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2184 Constraint = (),
2185 >,
2186 for<'de> crate::wire::SpiImplRegisterVmoRequest: ::fidl_next::Decode<
2187 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2188 Constraint = (),
2189 >,
2190 for<'de> crate::wire::SpiImplUnregisterVmoRequest: ::fidl_next::Decode<
2191 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2192 Constraint = (),
2193 >,
2194 for<'de> crate::wire::SpiImplReleaseRegisteredVmosRequest: ::fidl_next::Decode<
2195 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2196 Constraint = (),
2197 >,
2198 for<'de> crate::wire::SpiImplTransmitVmoRequest: ::fidl_next::Decode<
2199 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2200 Constraint = (),
2201 >,
2202 for<'de> crate::wire::SpiImplReceiveVmoRequest: ::fidl_next::Decode<
2203 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2204 Constraint = (),
2205 >,
2206 for<'de> crate::wire::SpiImplExchangeVmoRequest: ::fidl_next::Decode<
2207 <<___T as ::fidl_next::Transport>::RecvBuffer as ::fidl_next::AsDecoder<'de>>::Decoder,
2208 Constraint = (),
2209 >,
2210{
2211 async fn on_one_way(
2212 handler: &mut ___H,
2213 mut message: ::fidl_next::Message<___T>,
2214 ) -> ::core::result::Result<
2215 (),
2216 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
2217 > {
2218 match *message.header().ordinal {
2219 5302547493468731494 => match ::fidl_next::AsDecoderExt::into_decoded(message) {
2220 Ok(decoded) => {
2221 handler
2222 .release_registered_vmos(::fidl_next::Request::from_decoded(decoded))
2223 .await;
2224 Ok(())
2225 }
2226 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2227 ordinal: 5302547493468731494,
2228 error,
2229 }),
2230 },
2231
2232 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2233 }
2234 }
2235
2236 async fn on_two_way(
2237 handler: &mut ___H,
2238 mut message: ::fidl_next::Message<___T>,
2239 responder: ::fidl_next::protocol::Responder<___T>,
2240 ) -> ::core::result::Result<
2241 (),
2242 ::fidl_next::ProtocolError<<___T as ::fidl_next::Transport>::Error>,
2243 > {
2244 match *message.header().ordinal {
2245 4261972386852856527 => {
2246 let responder = ::fidl_next::Responder::from_untyped(responder);
2247
2248 handler.get_chip_select_count(responder).await;
2249 Ok(())
2250 }
2251
2252 7287789131276374998 => {
2253 let responder = ::fidl_next::Responder::from_untyped(responder);
2254
2255 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2256 Ok(decoded) => {
2257 handler
2258 .transmit_vector(::fidl_next::Request::from_decoded(decoded), responder)
2259 .await;
2260 Ok(())
2261 }
2262 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2263 ordinal: 7287789131276374998,
2264 error,
2265 }),
2266 }
2267 }
2268
2269 4813495552606122700 => {
2270 let responder = ::fidl_next::Responder::from_untyped(responder);
2271
2272 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2273 Ok(decoded) => {
2274 handler
2275 .receive_vector(::fidl_next::Request::from_decoded(decoded), responder)
2276 .await;
2277 Ok(())
2278 }
2279 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2280 ordinal: 4813495552606122700,
2281 error,
2282 }),
2283 }
2284 }
2285
2286 3844617764012354164 => {
2287 let responder = ::fidl_next::Responder::from_untyped(responder);
2288
2289 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2290 Ok(decoded) => {
2291 handler
2292 .exchange_vector(::fidl_next::Request::from_decoded(decoded), responder)
2293 .await;
2294 Ok(())
2295 }
2296 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2297 ordinal: 3844617764012354164,
2298 error,
2299 }),
2300 }
2301 }
2302
2303 9187537331803160557 => {
2304 let responder = ::fidl_next::Responder::from_untyped(responder);
2305
2306 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2307 Ok(decoded) => {
2308 handler
2309 .lock_bus(::fidl_next::Request::from_decoded(decoded), responder)
2310 .await;
2311 Ok(())
2312 }
2313 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2314 ordinal: 9187537331803160557,
2315 error,
2316 }),
2317 }
2318 }
2319
2320 3150764477565251378 => {
2321 let responder = ::fidl_next::Responder::from_untyped(responder);
2322
2323 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2324 Ok(decoded) => {
2325 handler
2326 .unlock_bus(::fidl_next::Request::from_decoded(decoded), responder)
2327 .await;
2328 Ok(())
2329 }
2330 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2331 ordinal: 3150764477565251378,
2332 error,
2333 }),
2334 }
2335 }
2336
2337 2270783649342134233 => {
2338 let responder = ::fidl_next::Responder::from_untyped(responder);
2339
2340 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2341 Ok(decoded) => {
2342 handler
2343 .register_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2344 .await;
2345 Ok(())
2346 }
2347 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2348 ordinal: 2270783649342134233,
2349 error,
2350 }),
2351 }
2352 }
2353
2354 8778583385931240091 => {
2355 let responder = ::fidl_next::Responder::from_untyped(responder);
2356
2357 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2358 Ok(decoded) => {
2359 handler
2360 .unregister_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2361 .await;
2362 Ok(())
2363 }
2364 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2365 ordinal: 8778583385931240091,
2366 error,
2367 }),
2368 }
2369 }
2370
2371 1490935665662854691 => {
2372 let responder = ::fidl_next::Responder::from_untyped(responder);
2373
2374 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2375 Ok(decoded) => {
2376 handler
2377 .transmit_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2378 .await;
2379 Ok(())
2380 }
2381 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2382 ordinal: 1490935665662854691,
2383 error,
2384 }),
2385 }
2386 }
2387
2388 7091744647492940488 => {
2389 let responder = ::fidl_next::Responder::from_untyped(responder);
2390
2391 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2392 Ok(decoded) => {
2393 handler
2394 .receive_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2395 .await;
2396 Ok(())
2397 }
2398 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2399 ordinal: 7091744647492940488,
2400 error,
2401 }),
2402 }
2403 }
2404
2405 3592177641282126076 => {
2406 let responder = ::fidl_next::Responder::from_untyped(responder);
2407
2408 match ::fidl_next::AsDecoderExt::into_decoded(message) {
2409 Ok(decoded) => {
2410 handler
2411 .exchange_vmo(::fidl_next::Request::from_decoded(decoded), responder)
2412 .await;
2413 Ok(())
2414 }
2415 Err(error) => Err(::fidl_next::ProtocolError::InvalidMessage {
2416 ordinal: 3592177641282126076,
2417 error,
2418 }),
2419 }
2420 }
2421
2422 ordinal => Err(::fidl_next::ProtocolError::UnknownOrdinal(ordinal)),
2423 }
2424 }
2425}
2426
2427impl<___T> SpiImplClientHandler<___T> for ::fidl_next::IgnoreEvents where
2428 ___T: ::fidl_next::Transport
2429{
2430}
2431
2432impl<___H, ___T> SpiImplLocalClientHandler<___T> for ::fidl_next::Local<___H>
2433where
2434 ___H: SpiImplClientHandler<___T>,
2435 ___T: ::fidl_next::Transport,
2436{
2437}
2438
2439impl<___H, ___T> SpiImplLocalServerHandler<___T> for ::fidl_next::Local<___H>
2440where
2441 ___H: SpiImplServerHandler<___T>,
2442 ___T: ::fidl_next::Transport,
2443{
2444 async fn get_chip_select_count(
2445 &mut self,
2446
2447 responder: ::fidl_next::Responder<spi_impl::GetChipSelectCount, ___T>,
2448 ) {
2449 ___H::get_chip_select_count(&mut self.0, responder).await
2450 }
2451
2452 async fn transmit_vector(
2453 &mut self,
2454
2455 request: ::fidl_next::Request<spi_impl::TransmitVector, ___T>,
2456
2457 responder: ::fidl_next::Responder<spi_impl::TransmitVector, ___T>,
2458 ) {
2459 ___H::transmit_vector(&mut self.0, request, responder).await
2460 }
2461
2462 async fn receive_vector(
2463 &mut self,
2464
2465 request: ::fidl_next::Request<spi_impl::ReceiveVector, ___T>,
2466
2467 responder: ::fidl_next::Responder<spi_impl::ReceiveVector, ___T>,
2468 ) {
2469 ___H::receive_vector(&mut self.0, request, responder).await
2470 }
2471
2472 async fn exchange_vector(
2473 &mut self,
2474
2475 request: ::fidl_next::Request<spi_impl::ExchangeVector, ___T>,
2476
2477 responder: ::fidl_next::Responder<spi_impl::ExchangeVector, ___T>,
2478 ) {
2479 ___H::exchange_vector(&mut self.0, request, responder).await
2480 }
2481
2482 async fn lock_bus(
2483 &mut self,
2484
2485 request: ::fidl_next::Request<spi_impl::LockBus, ___T>,
2486
2487 responder: ::fidl_next::Responder<spi_impl::LockBus, ___T>,
2488 ) {
2489 ___H::lock_bus(&mut self.0, request, responder).await
2490 }
2491
2492 async fn unlock_bus(
2493 &mut self,
2494
2495 request: ::fidl_next::Request<spi_impl::UnlockBus, ___T>,
2496
2497 responder: ::fidl_next::Responder<spi_impl::UnlockBus, ___T>,
2498 ) {
2499 ___H::unlock_bus(&mut self.0, request, responder).await
2500 }
2501
2502 async fn register_vmo(
2503 &mut self,
2504
2505 request: ::fidl_next::Request<spi_impl::RegisterVmo, ___T>,
2506
2507 responder: ::fidl_next::Responder<spi_impl::RegisterVmo, ___T>,
2508 ) {
2509 ___H::register_vmo(&mut self.0, request, responder).await
2510 }
2511
2512 async fn unregister_vmo(
2513 &mut self,
2514
2515 request: ::fidl_next::Request<spi_impl::UnregisterVmo, ___T>,
2516
2517 responder: ::fidl_next::Responder<spi_impl::UnregisterVmo, ___T>,
2518 ) {
2519 ___H::unregister_vmo(&mut self.0, request, responder).await
2520 }
2521
2522 async fn release_registered_vmos(
2523 &mut self,
2524
2525 request: ::fidl_next::Request<spi_impl::ReleaseRegisteredVmos, ___T>,
2526 ) {
2527 ___H::release_registered_vmos(&mut self.0, request).await
2528 }
2529
2530 async fn transmit_vmo(
2531 &mut self,
2532
2533 request: ::fidl_next::Request<spi_impl::TransmitVmo, ___T>,
2534
2535 responder: ::fidl_next::Responder<spi_impl::TransmitVmo, ___T>,
2536 ) {
2537 ___H::transmit_vmo(&mut self.0, request, responder).await
2538 }
2539
2540 async fn receive_vmo(
2541 &mut self,
2542
2543 request: ::fidl_next::Request<spi_impl::ReceiveVmo, ___T>,
2544
2545 responder: ::fidl_next::Responder<spi_impl::ReceiveVmo, ___T>,
2546 ) {
2547 ___H::receive_vmo(&mut self.0, request, responder).await
2548 }
2549
2550 async fn exchange_vmo(
2551 &mut self,
2552
2553 request: ::fidl_next::Request<spi_impl::ExchangeVmo, ___T>,
2554
2555 responder: ::fidl_next::Responder<spi_impl::ExchangeVmo, ___T>,
2556 ) {
2557 ___H::exchange_vmo(&mut self.0, request, responder).await
2558 }
2559}
2560
2561pub use fidl_next_common_fuchsia_hardware_spiimpl::*;