1#![warn(clippy::all)]
4#![allow(unused_parens, unused_mut, unused_imports, nonstandard_style)]
5
6use bitflags::bitflags;
7use fidl::client::QueryResponseFut;
8use fidl::encoding::{MessageBufFor, ProxyChannelBox, ResourceDialect};
9use fidl::endpoints::{ControlHandle as _, Responder as _};
10pub use fidl_fuchsia_hardware_vreg__common::*;
11use futures::future::{self, MaybeDone, TryFutureExt};
12use zx_status;
13
14#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
15pub struct VregMarker;
16
17impl fidl::endpoints::ProtocolMarker for VregMarker {
18 type Proxy = VregProxy;
19 type RequestStream = VregRequestStream;
20 #[cfg(target_os = "fuchsia")]
21 type SynchronousProxy = VregSynchronousProxy;
22
23 const DEBUG_NAME: &'static str = "fuchsia.hardware.vreg.Vreg";
24}
25impl fidl::endpoints::DiscoverableProtocolMarker for VregMarker {}
26pub type VregSetVoltageStepResult = Result<(), i32>;
27pub type VregGetVoltageStepResult = Result<u32, i32>;
28pub type VregSetStateResult = Result<(), i32>;
29pub type VregEnableResult = Result<(), i32>;
30pub type VregDisableResult = Result<(), i32>;
31pub type VregGetRegulatorParamsResult = Result<(u32, u32, u32), i32>;
32
33pub trait VregProxyInterface: Send + Sync {
34 type SetVoltageStepResponseFut: std::future::Future<Output = Result<VregSetVoltageStepResult, fidl::Error>>
35 + Send;
36 fn r#set_voltage_step(&self, step: u32) -> Self::SetVoltageStepResponseFut;
37 type GetVoltageStepResponseFut: std::future::Future<Output = Result<VregGetVoltageStepResult, fidl::Error>>
38 + Send;
39 fn r#get_voltage_step(&self) -> Self::GetVoltageStepResponseFut;
40 type SetStateResponseFut: std::future::Future<Output = Result<VregSetStateResult, fidl::Error>>
41 + Send;
42 fn r#set_state(&self, payload: &VregSetStateRequest) -> Self::SetStateResponseFut;
43 type EnableResponseFut: std::future::Future<Output = Result<VregEnableResult, fidl::Error>>
44 + Send;
45 fn r#enable(&self) -> Self::EnableResponseFut;
46 type DisableResponseFut: std::future::Future<Output = Result<VregDisableResult, fidl::Error>>
47 + Send;
48 fn r#disable(&self) -> Self::DisableResponseFut;
49 type GetRegulatorParamsResponseFut: std::future::Future<Output = Result<VregGetRegulatorParamsResult, fidl::Error>>
50 + Send;
51 fn r#get_regulator_params(&self) -> Self::GetRegulatorParamsResponseFut;
52}
53#[derive(Debug)]
54#[cfg(target_os = "fuchsia")]
55pub struct VregSynchronousProxy {
56 client: fidl::client::sync::Client,
57}
58
59#[cfg(target_os = "fuchsia")]
60impl fidl::endpoints::SynchronousProxy for VregSynchronousProxy {
61 type Proxy = VregProxy;
62 type Protocol = VregMarker;
63
64 fn from_channel(inner: fidl::Channel) -> Self {
65 Self::new(inner)
66 }
67
68 fn into_channel(self) -> fidl::Channel {
69 self.client.into_channel()
70 }
71
72 fn as_channel(&self) -> &fidl::Channel {
73 self.client.as_channel()
74 }
75}
76
77#[cfg(target_os = "fuchsia")]
78impl VregSynchronousProxy {
79 pub fn new(channel: fidl::Channel) -> Self {
80 Self { client: fidl::client::sync::Client::new(channel) }
81 }
82
83 pub fn into_channel(self) -> fidl::Channel {
84 self.client.into_channel()
85 }
86
87 pub fn wait_for_event(&self, deadline: zx::MonotonicInstant) -> Result<VregEvent, fidl::Error> {
90 VregEvent::decode(self.client.wait_for_event::<VregMarker>(deadline)?)
91 }
92
93 pub fn r#set_voltage_step(
94 &self,
95 mut step: u32,
96 ___deadline: zx::MonotonicInstant,
97 ) -> Result<VregSetVoltageStepResult, fidl::Error> {
98 let _response = self.client.send_query::<
99 VregSetVoltageStepRequest,
100 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
101 VregMarker,
102 >(
103 (step,),
104 0x89c04aa4d3929b9,
105 fidl::encoding::DynamicFlags::empty(),
106 ___deadline,
107 )?;
108 Ok(_response.map(|x| x))
109 }
110
111 pub fn r#get_voltage_step(
112 &self,
113 ___deadline: zx::MonotonicInstant,
114 ) -> Result<VregGetVoltageStepResult, fidl::Error> {
115 let _response = self.client.send_query::<
116 fidl::encoding::EmptyPayload,
117 fidl::encoding::ResultType<VregGetVoltageStepResponse, i32>,
118 VregMarker,
119 >(
120 (),
121 0x136c9faa076b55e1,
122 fidl::encoding::DynamicFlags::empty(),
123 ___deadline,
124 )?;
125 Ok(_response.map(|x| x.result))
126 }
127
128 pub fn r#set_state(
129 &self,
130 mut payload: &VregSetStateRequest,
131 ___deadline: zx::MonotonicInstant,
132 ) -> Result<VregSetStateResult, fidl::Error> {
133 let _response = self.client.send_query::<
134 VregSetStateRequest,
135 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
136 VregMarker,
137 >(
138 payload,
139 0x7fadd2556566a22e,
140 fidl::encoding::DynamicFlags::empty(),
141 ___deadline,
142 )?;
143 Ok(_response.map(|x| x))
144 }
145
146 pub fn r#enable(
147 &self,
148 ___deadline: zx::MonotonicInstant,
149 ) -> Result<VregEnableResult, fidl::Error> {
150 let _response = self.client.send_query::<
151 fidl::encoding::EmptyPayload,
152 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
153 VregMarker,
154 >(
155 (),
156 0xd2024213c6cde86,
157 fidl::encoding::DynamicFlags::empty(),
158 ___deadline,
159 )?;
160 Ok(_response.map(|x| x))
161 }
162
163 pub fn r#disable(
164 &self,
165 ___deadline: zx::MonotonicInstant,
166 ) -> Result<VregDisableResult, fidl::Error> {
167 let _response = self.client.send_query::<
168 fidl::encoding::EmptyPayload,
169 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
170 VregMarker,
171 >(
172 (),
173 0x61ba9b20b16637ad,
174 fidl::encoding::DynamicFlags::empty(),
175 ___deadline,
176 )?;
177 Ok(_response.map(|x| x))
178 }
179
180 pub fn r#get_regulator_params(
181 &self,
182 ___deadline: zx::MonotonicInstant,
183 ) -> Result<VregGetRegulatorParamsResult, fidl::Error> {
184 let _response = self.client.send_query::<
185 fidl::encoding::EmptyPayload,
186 fidl::encoding::ResultType<VregGetRegulatorParamsResponse, i32>,
187 VregMarker,
188 >(
189 (),
190 0x2336d00f8f794f8a,
191 fidl::encoding::DynamicFlags::empty(),
192 ___deadline,
193 )?;
194 Ok(_response.map(|x| (x.min_uv, x.step_size_uv, x.num_steps)))
195 }
196}
197
198#[cfg(target_os = "fuchsia")]
199impl From<VregSynchronousProxy> for zx::NullableHandle {
200 fn from(value: VregSynchronousProxy) -> Self {
201 value.into_channel().into()
202 }
203}
204
205#[cfg(target_os = "fuchsia")]
206impl From<fidl::Channel> for VregSynchronousProxy {
207 fn from(value: fidl::Channel) -> Self {
208 Self::new(value)
209 }
210}
211
212#[cfg(target_os = "fuchsia")]
213impl fidl::endpoints::FromClient for VregSynchronousProxy {
214 type Protocol = VregMarker;
215
216 fn from_client(value: fidl::endpoints::ClientEnd<VregMarker>) -> Self {
217 Self::new(value.into_channel())
218 }
219}
220
221#[derive(Debug, Clone)]
222pub struct VregProxy {
223 client: fidl::client::Client<fidl::encoding::DefaultFuchsiaResourceDialect>,
224}
225
226impl fidl::endpoints::Proxy for VregProxy {
227 type Protocol = VregMarker;
228
229 fn from_channel(inner: ::fidl::AsyncChannel) -> Self {
230 Self::new(inner)
231 }
232
233 fn into_channel(self) -> Result<::fidl::AsyncChannel, Self> {
234 self.client.into_channel().map_err(|client| Self { client })
235 }
236
237 fn as_channel(&self) -> &::fidl::AsyncChannel {
238 self.client.as_channel()
239 }
240}
241
242impl VregProxy {
243 pub fn new(channel: ::fidl::AsyncChannel) -> Self {
245 let protocol_name = <VregMarker as fidl::endpoints::ProtocolMarker>::DEBUG_NAME;
246 Self { client: fidl::client::Client::new(channel, protocol_name) }
247 }
248
249 pub fn take_event_stream(&self) -> VregEventStream {
255 VregEventStream { event_receiver: self.client.take_event_receiver() }
256 }
257
258 pub fn r#set_voltage_step(
259 &self,
260 mut step: u32,
261 ) -> fidl::client::QueryResponseFut<
262 VregSetVoltageStepResult,
263 fidl::encoding::DefaultFuchsiaResourceDialect,
264 > {
265 VregProxyInterface::r#set_voltage_step(self, step)
266 }
267
268 pub fn r#get_voltage_step(
269 &self,
270 ) -> fidl::client::QueryResponseFut<
271 VregGetVoltageStepResult,
272 fidl::encoding::DefaultFuchsiaResourceDialect,
273 > {
274 VregProxyInterface::r#get_voltage_step(self)
275 }
276
277 pub fn r#set_state(
278 &self,
279 mut payload: &VregSetStateRequest,
280 ) -> fidl::client::QueryResponseFut<
281 VregSetStateResult,
282 fidl::encoding::DefaultFuchsiaResourceDialect,
283 > {
284 VregProxyInterface::r#set_state(self, payload)
285 }
286
287 pub fn r#enable(
288 &self,
289 ) -> fidl::client::QueryResponseFut<
290 VregEnableResult,
291 fidl::encoding::DefaultFuchsiaResourceDialect,
292 > {
293 VregProxyInterface::r#enable(self)
294 }
295
296 pub fn r#disable(
297 &self,
298 ) -> fidl::client::QueryResponseFut<
299 VregDisableResult,
300 fidl::encoding::DefaultFuchsiaResourceDialect,
301 > {
302 VregProxyInterface::r#disable(self)
303 }
304
305 pub fn r#get_regulator_params(
306 &self,
307 ) -> fidl::client::QueryResponseFut<
308 VregGetRegulatorParamsResult,
309 fidl::encoding::DefaultFuchsiaResourceDialect,
310 > {
311 VregProxyInterface::r#get_regulator_params(self)
312 }
313}
314
315impl VregProxyInterface for VregProxy {
316 type SetVoltageStepResponseFut = fidl::client::QueryResponseFut<
317 VregSetVoltageStepResult,
318 fidl::encoding::DefaultFuchsiaResourceDialect,
319 >;
320 fn r#set_voltage_step(&self, mut step: u32) -> Self::SetVoltageStepResponseFut {
321 fn _decode(
322 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
323 ) -> Result<VregSetVoltageStepResult, fidl::Error> {
324 let _response = fidl::client::decode_transaction_body::<
325 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
326 fidl::encoding::DefaultFuchsiaResourceDialect,
327 0x89c04aa4d3929b9,
328 >(_buf?)?;
329 Ok(_response.map(|x| x))
330 }
331 self.client.send_query_and_decode::<VregSetVoltageStepRequest, VregSetVoltageStepResult>(
332 (step,),
333 0x89c04aa4d3929b9,
334 fidl::encoding::DynamicFlags::empty(),
335 _decode,
336 )
337 }
338
339 type GetVoltageStepResponseFut = fidl::client::QueryResponseFut<
340 VregGetVoltageStepResult,
341 fidl::encoding::DefaultFuchsiaResourceDialect,
342 >;
343 fn r#get_voltage_step(&self) -> Self::GetVoltageStepResponseFut {
344 fn _decode(
345 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
346 ) -> Result<VregGetVoltageStepResult, fidl::Error> {
347 let _response = fidl::client::decode_transaction_body::<
348 fidl::encoding::ResultType<VregGetVoltageStepResponse, i32>,
349 fidl::encoding::DefaultFuchsiaResourceDialect,
350 0x136c9faa076b55e1,
351 >(_buf?)?;
352 Ok(_response.map(|x| x.result))
353 }
354 self.client.send_query_and_decode::<fidl::encoding::EmptyPayload, VregGetVoltageStepResult>(
355 (),
356 0x136c9faa076b55e1,
357 fidl::encoding::DynamicFlags::empty(),
358 _decode,
359 )
360 }
361
362 type SetStateResponseFut = fidl::client::QueryResponseFut<
363 VregSetStateResult,
364 fidl::encoding::DefaultFuchsiaResourceDialect,
365 >;
366 fn r#set_state(&self, mut payload: &VregSetStateRequest) -> Self::SetStateResponseFut {
367 fn _decode(
368 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
369 ) -> Result<VregSetStateResult, fidl::Error> {
370 let _response = fidl::client::decode_transaction_body::<
371 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
372 fidl::encoding::DefaultFuchsiaResourceDialect,
373 0x7fadd2556566a22e,
374 >(_buf?)?;
375 Ok(_response.map(|x| x))
376 }
377 self.client.send_query_and_decode::<VregSetStateRequest, VregSetStateResult>(
378 payload,
379 0x7fadd2556566a22e,
380 fidl::encoding::DynamicFlags::empty(),
381 _decode,
382 )
383 }
384
385 type EnableResponseFut = fidl::client::QueryResponseFut<
386 VregEnableResult,
387 fidl::encoding::DefaultFuchsiaResourceDialect,
388 >;
389 fn r#enable(&self) -> Self::EnableResponseFut {
390 fn _decode(
391 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
392 ) -> Result<VregEnableResult, fidl::Error> {
393 let _response = fidl::client::decode_transaction_body::<
394 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
395 fidl::encoding::DefaultFuchsiaResourceDialect,
396 0xd2024213c6cde86,
397 >(_buf?)?;
398 Ok(_response.map(|x| x))
399 }
400 self.client.send_query_and_decode::<fidl::encoding::EmptyPayload, VregEnableResult>(
401 (),
402 0xd2024213c6cde86,
403 fidl::encoding::DynamicFlags::empty(),
404 _decode,
405 )
406 }
407
408 type DisableResponseFut = fidl::client::QueryResponseFut<
409 VregDisableResult,
410 fidl::encoding::DefaultFuchsiaResourceDialect,
411 >;
412 fn r#disable(&self) -> Self::DisableResponseFut {
413 fn _decode(
414 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
415 ) -> Result<VregDisableResult, fidl::Error> {
416 let _response = fidl::client::decode_transaction_body::<
417 fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>,
418 fidl::encoding::DefaultFuchsiaResourceDialect,
419 0x61ba9b20b16637ad,
420 >(_buf?)?;
421 Ok(_response.map(|x| x))
422 }
423 self.client.send_query_and_decode::<fidl::encoding::EmptyPayload, VregDisableResult>(
424 (),
425 0x61ba9b20b16637ad,
426 fidl::encoding::DynamicFlags::empty(),
427 _decode,
428 )
429 }
430
431 type GetRegulatorParamsResponseFut = fidl::client::QueryResponseFut<
432 VregGetRegulatorParamsResult,
433 fidl::encoding::DefaultFuchsiaResourceDialect,
434 >;
435 fn r#get_regulator_params(&self) -> Self::GetRegulatorParamsResponseFut {
436 fn _decode(
437 mut _buf: Result<<fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc, fidl::Error>,
438 ) -> Result<VregGetRegulatorParamsResult, fidl::Error> {
439 let _response = fidl::client::decode_transaction_body::<
440 fidl::encoding::ResultType<VregGetRegulatorParamsResponse, i32>,
441 fidl::encoding::DefaultFuchsiaResourceDialect,
442 0x2336d00f8f794f8a,
443 >(_buf?)?;
444 Ok(_response.map(|x| (x.min_uv, x.step_size_uv, x.num_steps)))
445 }
446 self.client
447 .send_query_and_decode::<fidl::encoding::EmptyPayload, VregGetRegulatorParamsResult>(
448 (),
449 0x2336d00f8f794f8a,
450 fidl::encoding::DynamicFlags::empty(),
451 _decode,
452 )
453 }
454}
455
456pub struct VregEventStream {
457 event_receiver: fidl::client::EventReceiver<fidl::encoding::DefaultFuchsiaResourceDialect>,
458}
459
460impl std::marker::Unpin for VregEventStream {}
461
462impl futures::stream::FusedStream for VregEventStream {
463 fn is_terminated(&self) -> bool {
464 self.event_receiver.is_terminated()
465 }
466}
467
468impl futures::Stream for VregEventStream {
469 type Item = Result<VregEvent, fidl::Error>;
470
471 fn poll_next(
472 mut self: std::pin::Pin<&mut Self>,
473 cx: &mut std::task::Context<'_>,
474 ) -> std::task::Poll<Option<Self::Item>> {
475 match futures::ready!(futures::stream::StreamExt::poll_next_unpin(
476 &mut self.event_receiver,
477 cx
478 )?) {
479 Some(buf) => std::task::Poll::Ready(Some(VregEvent::decode(buf))),
480 None => std::task::Poll::Ready(None),
481 }
482 }
483}
484
485#[derive(Debug)]
486pub enum VregEvent {}
487
488impl VregEvent {
489 fn decode(
491 mut buf: <fidl::encoding::DefaultFuchsiaResourceDialect as fidl::encoding::ResourceDialect>::MessageBufEtc,
492 ) -> Result<VregEvent, fidl::Error> {
493 let (bytes, _handles) = buf.split_mut();
494 let (tx_header, _body_bytes) = fidl::encoding::decode_transaction_header(bytes)?;
495 debug_assert_eq!(tx_header.tx_id, 0);
496 match tx_header.ordinal {
497 _ => Err(fidl::Error::UnknownOrdinal {
498 ordinal: tx_header.ordinal,
499 protocol_name: <VregMarker as fidl::endpoints::ProtocolMarker>::DEBUG_NAME,
500 }),
501 }
502 }
503}
504
505pub struct VregRequestStream {
507 inner: std::sync::Arc<fidl::ServeInner<fidl::encoding::DefaultFuchsiaResourceDialect>>,
508 is_terminated: bool,
509}
510
511impl std::marker::Unpin for VregRequestStream {}
512
513impl futures::stream::FusedStream for VregRequestStream {
514 fn is_terminated(&self) -> bool {
515 self.is_terminated
516 }
517}
518
519impl fidl::endpoints::RequestStream for VregRequestStream {
520 type Protocol = VregMarker;
521 type ControlHandle = VregControlHandle;
522
523 fn from_channel(channel: ::fidl::AsyncChannel) -> Self {
524 Self { inner: std::sync::Arc::new(fidl::ServeInner::new(channel)), is_terminated: false }
525 }
526
527 fn control_handle(&self) -> Self::ControlHandle {
528 VregControlHandle { inner: self.inner.clone() }
529 }
530
531 fn into_inner(
532 self,
533 ) -> (::std::sync::Arc<fidl::ServeInner<fidl::encoding::DefaultFuchsiaResourceDialect>>, bool)
534 {
535 (self.inner, self.is_terminated)
536 }
537
538 fn from_inner(
539 inner: std::sync::Arc<fidl::ServeInner<fidl::encoding::DefaultFuchsiaResourceDialect>>,
540 is_terminated: bool,
541 ) -> Self {
542 Self { inner, is_terminated }
543 }
544}
545
546impl futures::Stream for VregRequestStream {
547 type Item = Result<VregRequest, fidl::Error>;
548
549 fn poll_next(
550 mut self: std::pin::Pin<&mut Self>,
551 cx: &mut std::task::Context<'_>,
552 ) -> std::task::Poll<Option<Self::Item>> {
553 let this = &mut *self;
554 if this.inner.check_shutdown(cx) {
555 this.is_terminated = true;
556 return std::task::Poll::Ready(None);
557 }
558 if this.is_terminated {
559 panic!("polled VregRequestStream after completion");
560 }
561 fidl::encoding::with_tls_decode_buf::<_, fidl::encoding::DefaultFuchsiaResourceDialect>(
562 |bytes, handles| {
563 match this.inner.channel().read_etc(cx, bytes, handles) {
564 std::task::Poll::Ready(Ok(())) => {}
565 std::task::Poll::Pending => return std::task::Poll::Pending,
566 std::task::Poll::Ready(Err(zx_status::Status::PEER_CLOSED)) => {
567 this.is_terminated = true;
568 return std::task::Poll::Ready(None);
569 }
570 std::task::Poll::Ready(Err(e)) => {
571 return std::task::Poll::Ready(Some(Err(fidl::Error::ServerRequestRead(
572 e.into(),
573 ))));
574 }
575 }
576
577 let (header, _body_bytes) = fidl::encoding::decode_transaction_header(bytes)?;
579
580 std::task::Poll::Ready(Some(match header.ordinal {
581 0x89c04aa4d3929b9 => {
582 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
583 let mut req = fidl::new_empty!(
584 VregSetVoltageStepRequest,
585 fidl::encoding::DefaultFuchsiaResourceDialect
586 );
587 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<VregSetVoltageStepRequest>(&header, _body_bytes, handles, &mut req)?;
588 let control_handle = VregControlHandle { inner: this.inner.clone() };
589 Ok(VregRequest::SetVoltageStep {
590 step: req.step,
591
592 responder: VregSetVoltageStepResponder {
593 control_handle: std::mem::ManuallyDrop::new(control_handle),
594 tx_id: header.tx_id,
595 },
596 })
597 }
598 0x136c9faa076b55e1 => {
599 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
600 let mut req = fidl::new_empty!(
601 fidl::encoding::EmptyPayload,
602 fidl::encoding::DefaultFuchsiaResourceDialect
603 );
604 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<fidl::encoding::EmptyPayload>(&header, _body_bytes, handles, &mut req)?;
605 let control_handle = VregControlHandle { inner: this.inner.clone() };
606 Ok(VregRequest::GetVoltageStep {
607 responder: VregGetVoltageStepResponder {
608 control_handle: std::mem::ManuallyDrop::new(control_handle),
609 tx_id: header.tx_id,
610 },
611 })
612 }
613 0x7fadd2556566a22e => {
614 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
615 let mut req = fidl::new_empty!(
616 VregSetStateRequest,
617 fidl::encoding::DefaultFuchsiaResourceDialect
618 );
619 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<VregSetStateRequest>(&header, _body_bytes, handles, &mut req)?;
620 let control_handle = VregControlHandle { inner: this.inner.clone() };
621 Ok(VregRequest::SetState {
622 payload: req,
623 responder: VregSetStateResponder {
624 control_handle: std::mem::ManuallyDrop::new(control_handle),
625 tx_id: header.tx_id,
626 },
627 })
628 }
629 0xd2024213c6cde86 => {
630 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
631 let mut req = fidl::new_empty!(
632 fidl::encoding::EmptyPayload,
633 fidl::encoding::DefaultFuchsiaResourceDialect
634 );
635 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<fidl::encoding::EmptyPayload>(&header, _body_bytes, handles, &mut req)?;
636 let control_handle = VregControlHandle { inner: this.inner.clone() };
637 Ok(VregRequest::Enable {
638 responder: VregEnableResponder {
639 control_handle: std::mem::ManuallyDrop::new(control_handle),
640 tx_id: header.tx_id,
641 },
642 })
643 }
644 0x61ba9b20b16637ad => {
645 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
646 let mut req = fidl::new_empty!(
647 fidl::encoding::EmptyPayload,
648 fidl::encoding::DefaultFuchsiaResourceDialect
649 );
650 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<fidl::encoding::EmptyPayload>(&header, _body_bytes, handles, &mut req)?;
651 let control_handle = VregControlHandle { inner: this.inner.clone() };
652 Ok(VregRequest::Disable {
653 responder: VregDisableResponder {
654 control_handle: std::mem::ManuallyDrop::new(control_handle),
655 tx_id: header.tx_id,
656 },
657 })
658 }
659 0x2336d00f8f794f8a => {
660 header.validate_request_tx_id(fidl::MethodType::TwoWay)?;
661 let mut req = fidl::new_empty!(
662 fidl::encoding::EmptyPayload,
663 fidl::encoding::DefaultFuchsiaResourceDialect
664 );
665 fidl::encoding::Decoder::<fidl::encoding::DefaultFuchsiaResourceDialect>::decode_into::<fidl::encoding::EmptyPayload>(&header, _body_bytes, handles, &mut req)?;
666 let control_handle = VregControlHandle { inner: this.inner.clone() };
667 Ok(VregRequest::GetRegulatorParams {
668 responder: VregGetRegulatorParamsResponder {
669 control_handle: std::mem::ManuallyDrop::new(control_handle),
670 tx_id: header.tx_id,
671 },
672 })
673 }
674 _ => Err(fidl::Error::UnknownOrdinal {
675 ordinal: header.ordinal,
676 protocol_name: <VregMarker as fidl::endpoints::ProtocolMarker>::DEBUG_NAME,
677 }),
678 }))
679 },
680 )
681 }
682}
683
684#[derive(Debug)]
685pub enum VregRequest {
686 SetVoltageStep { step: u32, responder: VregSetVoltageStepResponder },
687 GetVoltageStep { responder: VregGetVoltageStepResponder },
688 SetState { payload: VregSetStateRequest, responder: VregSetStateResponder },
689 Enable { responder: VregEnableResponder },
690 Disable { responder: VregDisableResponder },
691 GetRegulatorParams { responder: VregGetRegulatorParamsResponder },
692}
693
694impl VregRequest {
695 #[allow(irrefutable_let_patterns)]
696 pub fn into_set_voltage_step(self) -> Option<(u32, VregSetVoltageStepResponder)> {
697 if let VregRequest::SetVoltageStep { step, responder } = self {
698 Some((step, responder))
699 } else {
700 None
701 }
702 }
703
704 #[allow(irrefutable_let_patterns)]
705 pub fn into_get_voltage_step(self) -> Option<(VregGetVoltageStepResponder)> {
706 if let VregRequest::GetVoltageStep { responder } = self { Some((responder)) } else { None }
707 }
708
709 #[allow(irrefutable_let_patterns)]
710 pub fn into_set_state(self) -> Option<(VregSetStateRequest, VregSetStateResponder)> {
711 if let VregRequest::SetState { payload, responder } = self {
712 Some((payload, responder))
713 } else {
714 None
715 }
716 }
717
718 #[allow(irrefutable_let_patterns)]
719 pub fn into_enable(self) -> Option<(VregEnableResponder)> {
720 if let VregRequest::Enable { responder } = self { Some((responder)) } else { None }
721 }
722
723 #[allow(irrefutable_let_patterns)]
724 pub fn into_disable(self) -> Option<(VregDisableResponder)> {
725 if let VregRequest::Disable { responder } = self { Some((responder)) } else { None }
726 }
727
728 #[allow(irrefutable_let_patterns)]
729 pub fn into_get_regulator_params(self) -> Option<(VregGetRegulatorParamsResponder)> {
730 if let VregRequest::GetRegulatorParams { responder } = self {
731 Some((responder))
732 } else {
733 None
734 }
735 }
736
737 pub fn method_name(&self) -> &'static str {
739 match *self {
740 VregRequest::SetVoltageStep { .. } => "set_voltage_step",
741 VregRequest::GetVoltageStep { .. } => "get_voltage_step",
742 VregRequest::SetState { .. } => "set_state",
743 VregRequest::Enable { .. } => "enable",
744 VregRequest::Disable { .. } => "disable",
745 VregRequest::GetRegulatorParams { .. } => "get_regulator_params",
746 }
747 }
748}
749
750#[derive(Debug, Clone)]
751pub struct VregControlHandle {
752 inner: std::sync::Arc<fidl::ServeInner<fidl::encoding::DefaultFuchsiaResourceDialect>>,
753}
754
755impl fidl::endpoints::ControlHandle for VregControlHandle {
756 fn shutdown(&self) {
757 self.inner.shutdown()
758 }
759
760 fn shutdown_with_epitaph(&self, status: zx_status::Status) {
761 self.inner.shutdown_with_epitaph(status)
762 }
763
764 fn is_closed(&self) -> bool {
765 self.inner.channel().is_closed()
766 }
767 fn on_closed(&self) -> fidl::OnSignalsRef<'_> {
768 self.inner.channel().on_closed()
769 }
770
771 #[cfg(target_os = "fuchsia")]
772 fn signal_peer(
773 &self,
774 clear_mask: zx::Signals,
775 set_mask: zx::Signals,
776 ) -> Result<(), zx_status::Status> {
777 use fidl::Peered;
778 self.inner.channel().signal_peer(clear_mask, set_mask)
779 }
780}
781
782impl VregControlHandle {}
783
784#[must_use = "FIDL methods require a response to be sent"]
785#[derive(Debug)]
786pub struct VregSetVoltageStepResponder {
787 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
788 tx_id: u32,
789}
790
791impl std::ops::Drop for VregSetVoltageStepResponder {
795 fn drop(&mut self) {
796 self.control_handle.shutdown();
797 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
799 }
800}
801
802impl fidl::endpoints::Responder for VregSetVoltageStepResponder {
803 type ControlHandle = VregControlHandle;
804
805 fn control_handle(&self) -> &VregControlHandle {
806 &self.control_handle
807 }
808
809 fn drop_without_shutdown(mut self) {
810 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
812 std::mem::forget(self);
814 }
815}
816
817impl VregSetVoltageStepResponder {
818 pub fn send(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
822 let _result = self.send_raw(result);
823 if _result.is_err() {
824 self.control_handle.shutdown();
825 }
826 self.drop_without_shutdown();
827 _result
828 }
829
830 pub fn send_no_shutdown_on_err(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
832 let _result = self.send_raw(result);
833 self.drop_without_shutdown();
834 _result
835 }
836
837 fn send_raw(&self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
838 self.control_handle
839 .inner
840 .send::<fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>>(
841 result,
842 self.tx_id,
843 0x89c04aa4d3929b9,
844 fidl::encoding::DynamicFlags::empty(),
845 )
846 }
847}
848
849#[must_use = "FIDL methods require a response to be sent"]
850#[derive(Debug)]
851pub struct VregGetVoltageStepResponder {
852 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
853 tx_id: u32,
854}
855
856impl std::ops::Drop for VregGetVoltageStepResponder {
860 fn drop(&mut self) {
861 self.control_handle.shutdown();
862 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
864 }
865}
866
867impl fidl::endpoints::Responder for VregGetVoltageStepResponder {
868 type ControlHandle = VregControlHandle;
869
870 fn control_handle(&self) -> &VregControlHandle {
871 &self.control_handle
872 }
873
874 fn drop_without_shutdown(mut self) {
875 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
877 std::mem::forget(self);
879 }
880}
881
882impl VregGetVoltageStepResponder {
883 pub fn send(self, mut result: Result<u32, i32>) -> Result<(), fidl::Error> {
887 let _result = self.send_raw(result);
888 if _result.is_err() {
889 self.control_handle.shutdown();
890 }
891 self.drop_without_shutdown();
892 _result
893 }
894
895 pub fn send_no_shutdown_on_err(self, mut result: Result<u32, i32>) -> Result<(), fidl::Error> {
897 let _result = self.send_raw(result);
898 self.drop_without_shutdown();
899 _result
900 }
901
902 fn send_raw(&self, mut result: Result<u32, i32>) -> Result<(), fidl::Error> {
903 self.control_handle
904 .inner
905 .send::<fidl::encoding::ResultType<VregGetVoltageStepResponse, i32>>(
906 result.map(|result| (result,)),
907 self.tx_id,
908 0x136c9faa076b55e1,
909 fidl::encoding::DynamicFlags::empty(),
910 )
911 }
912}
913
914#[must_use = "FIDL methods require a response to be sent"]
915#[derive(Debug)]
916pub struct VregSetStateResponder {
917 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
918 tx_id: u32,
919}
920
921impl std::ops::Drop for VregSetStateResponder {
925 fn drop(&mut self) {
926 self.control_handle.shutdown();
927 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
929 }
930}
931
932impl fidl::endpoints::Responder for VregSetStateResponder {
933 type ControlHandle = VregControlHandle;
934
935 fn control_handle(&self) -> &VregControlHandle {
936 &self.control_handle
937 }
938
939 fn drop_without_shutdown(mut self) {
940 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
942 std::mem::forget(self);
944 }
945}
946
947impl VregSetStateResponder {
948 pub fn send(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
952 let _result = self.send_raw(result);
953 if _result.is_err() {
954 self.control_handle.shutdown();
955 }
956 self.drop_without_shutdown();
957 _result
958 }
959
960 pub fn send_no_shutdown_on_err(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
962 let _result = self.send_raw(result);
963 self.drop_without_shutdown();
964 _result
965 }
966
967 fn send_raw(&self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
968 self.control_handle
969 .inner
970 .send::<fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>>(
971 result,
972 self.tx_id,
973 0x7fadd2556566a22e,
974 fidl::encoding::DynamicFlags::empty(),
975 )
976 }
977}
978
979#[must_use = "FIDL methods require a response to be sent"]
980#[derive(Debug)]
981pub struct VregEnableResponder {
982 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
983 tx_id: u32,
984}
985
986impl std::ops::Drop for VregEnableResponder {
990 fn drop(&mut self) {
991 self.control_handle.shutdown();
992 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
994 }
995}
996
997impl fidl::endpoints::Responder for VregEnableResponder {
998 type ControlHandle = VregControlHandle;
999
1000 fn control_handle(&self) -> &VregControlHandle {
1001 &self.control_handle
1002 }
1003
1004 fn drop_without_shutdown(mut self) {
1005 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
1007 std::mem::forget(self);
1009 }
1010}
1011
1012impl VregEnableResponder {
1013 pub fn send(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1017 let _result = self.send_raw(result);
1018 if _result.is_err() {
1019 self.control_handle.shutdown();
1020 }
1021 self.drop_without_shutdown();
1022 _result
1023 }
1024
1025 pub fn send_no_shutdown_on_err(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1027 let _result = self.send_raw(result);
1028 self.drop_without_shutdown();
1029 _result
1030 }
1031
1032 fn send_raw(&self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1033 self.control_handle
1034 .inner
1035 .send::<fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>>(
1036 result,
1037 self.tx_id,
1038 0xd2024213c6cde86,
1039 fidl::encoding::DynamicFlags::empty(),
1040 )
1041 }
1042}
1043
1044#[must_use = "FIDL methods require a response to be sent"]
1045#[derive(Debug)]
1046pub struct VregDisableResponder {
1047 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
1048 tx_id: u32,
1049}
1050
1051impl std::ops::Drop for VregDisableResponder {
1055 fn drop(&mut self) {
1056 self.control_handle.shutdown();
1057 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
1059 }
1060}
1061
1062impl fidl::endpoints::Responder for VregDisableResponder {
1063 type ControlHandle = VregControlHandle;
1064
1065 fn control_handle(&self) -> &VregControlHandle {
1066 &self.control_handle
1067 }
1068
1069 fn drop_without_shutdown(mut self) {
1070 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
1072 std::mem::forget(self);
1074 }
1075}
1076
1077impl VregDisableResponder {
1078 pub fn send(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1082 let _result = self.send_raw(result);
1083 if _result.is_err() {
1084 self.control_handle.shutdown();
1085 }
1086 self.drop_without_shutdown();
1087 _result
1088 }
1089
1090 pub fn send_no_shutdown_on_err(self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1092 let _result = self.send_raw(result);
1093 self.drop_without_shutdown();
1094 _result
1095 }
1096
1097 fn send_raw(&self, mut result: Result<(), i32>) -> Result<(), fidl::Error> {
1098 self.control_handle
1099 .inner
1100 .send::<fidl::encoding::ResultType<fidl::encoding::EmptyStruct, i32>>(
1101 result,
1102 self.tx_id,
1103 0x61ba9b20b16637ad,
1104 fidl::encoding::DynamicFlags::empty(),
1105 )
1106 }
1107}
1108
1109#[must_use = "FIDL methods require a response to be sent"]
1110#[derive(Debug)]
1111pub struct VregGetRegulatorParamsResponder {
1112 control_handle: std::mem::ManuallyDrop<VregControlHandle>,
1113 tx_id: u32,
1114}
1115
1116impl std::ops::Drop for VregGetRegulatorParamsResponder {
1120 fn drop(&mut self) {
1121 self.control_handle.shutdown();
1122 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
1124 }
1125}
1126
1127impl fidl::endpoints::Responder for VregGetRegulatorParamsResponder {
1128 type ControlHandle = VregControlHandle;
1129
1130 fn control_handle(&self) -> &VregControlHandle {
1131 &self.control_handle
1132 }
1133
1134 fn drop_without_shutdown(mut self) {
1135 unsafe { std::mem::ManuallyDrop::drop(&mut self.control_handle) };
1137 std::mem::forget(self);
1139 }
1140}
1141
1142impl VregGetRegulatorParamsResponder {
1143 pub fn send(self, mut result: Result<(u32, u32, u32), i32>) -> Result<(), fidl::Error> {
1147 let _result = self.send_raw(result);
1148 if _result.is_err() {
1149 self.control_handle.shutdown();
1150 }
1151 self.drop_without_shutdown();
1152 _result
1153 }
1154
1155 pub fn send_no_shutdown_on_err(
1157 self,
1158 mut result: Result<(u32, u32, u32), i32>,
1159 ) -> Result<(), fidl::Error> {
1160 let _result = self.send_raw(result);
1161 self.drop_without_shutdown();
1162 _result
1163 }
1164
1165 fn send_raw(&self, mut result: Result<(u32, u32, u32), i32>) -> Result<(), fidl::Error> {
1166 self.control_handle
1167 .inner
1168 .send::<fidl::encoding::ResultType<VregGetRegulatorParamsResponse, i32>>(
1169 result,
1170 self.tx_id,
1171 0x2336d00f8f794f8a,
1172 fidl::encoding::DynamicFlags::empty(),
1173 )
1174 }
1175}
1176
1177#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
1178pub struct ServiceMarker;
1179
1180#[cfg(target_os = "fuchsia")]
1181impl fidl::endpoints::ServiceMarker for ServiceMarker {
1182 type Proxy = ServiceProxy;
1183 type Request = ServiceRequest;
1184 const SERVICE_NAME: &'static str = "fuchsia.hardware.vreg.Service";
1185}
1186
1187#[cfg(target_os = "fuchsia")]
1190pub enum ServiceRequest {
1191 Vreg(VregRequestStream),
1192}
1193
1194#[cfg(target_os = "fuchsia")]
1195impl fidl::endpoints::ServiceRequest for ServiceRequest {
1196 type Service = ServiceMarker;
1197
1198 fn dispatch(name: &str, _channel: fidl::AsyncChannel) -> Self {
1199 match name {
1200 "vreg" => Self::Vreg(
1201 <VregRequestStream as fidl::endpoints::RequestStream>::from_channel(_channel),
1202 ),
1203 _ => panic!("no such member protocol name for service Service"),
1204 }
1205 }
1206
1207 fn member_names() -> &'static [&'static str] {
1208 &["vreg"]
1209 }
1210}
1211#[cfg(target_os = "fuchsia")]
1212pub struct ServiceProxy(#[allow(dead_code)] Box<dyn fidl::endpoints::MemberOpener>);
1213
1214#[cfg(target_os = "fuchsia")]
1215impl fidl::endpoints::ServiceProxy for ServiceProxy {
1216 type Service = ServiceMarker;
1217
1218 fn from_member_opener(opener: Box<dyn fidl::endpoints::MemberOpener>) -> Self {
1219 Self(opener)
1220 }
1221}
1222
1223#[cfg(target_os = "fuchsia")]
1224impl ServiceProxy {
1225 pub fn connect_to_vreg(&self) -> Result<VregProxy, fidl::Error> {
1226 let (proxy, server_end) = fidl::endpoints::create_proxy::<VregMarker>();
1227 self.connect_channel_to_vreg(server_end)?;
1228 Ok(proxy)
1229 }
1230
1231 pub fn connect_to_vreg_sync(&self) -> Result<VregSynchronousProxy, fidl::Error> {
1234 let (proxy, server_end) = fidl::endpoints::create_sync_proxy::<VregMarker>();
1235 self.connect_channel_to_vreg(server_end)?;
1236 Ok(proxy)
1237 }
1238
1239 pub fn connect_channel_to_vreg(
1242 &self,
1243 server_end: fidl::endpoints::ServerEnd<VregMarker>,
1244 ) -> Result<(), fidl::Error> {
1245 self.0.open_member("vreg", server_end.into_channel())
1246 }
1247
1248 pub fn instance_name(&self) -> &str {
1249 self.0.instance_name()
1250 }
1251}
1252
1253mod internal {
1254 use super::*;
1255}