fidl_data_zx/
port.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zx` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use zerocopy::{FromBytes, IntoBytes};
11
12use crate::types::*;
13use crate::zx_common::*;
14
15#[repr(C)]
16#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
17pub struct PacketSignal {
18    pub trigger: Signals,
19    pub observed: Signals,
20    pub count: u64,
21    pub timestamp: Time,
22    pub reserved1: u64,
23}
24
25#[repr(C)]
26#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
27pub struct PacketException {
28    pub pid: u64,
29    pub tid: u64,
30    pub reserved0: u64,
31    pub reserved1: u64,
32}
33
34#[repr(C)]
35#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
36pub struct PacketGuestBell {
37    pub addr: Gpaddr,
38    pub reserved0: u64,
39    pub reserved1: u64,
40    pub reserved2: u64,
41}
42
43#[repr(C)]
44#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
45pub struct PacketGuestMem {
46    pub addr: Gpaddr,
47}
48
49#[repr(C)]
50#[derive(Clone, Copy, Debug, Eq, PartialEq)]
51pub struct PacketGuestIo {
52    pub port: u16,
53    pub access_size: u8,
54    pub input: bool,
55    pub reserved0: u64,
56    pub reserved1: u64,
57    pub reserved2: u64,
58}
59
60#[repr(C)]
61#[derive(Clone, Copy, Debug, Eq, PartialEq)]
62pub struct PacketGuestVcpu {
63    pub r#type: u8,
64    pub reserved: u64,
65}
66
67#[repr(C)]
68#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
69pub struct PacketInterrupt {
70    pub timestamp: Time,
71    pub reserved0: u64,
72    pub reserved1: u64,
73    pub reserved2: u64,
74}
75
76#[repr(C)]
77#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
78pub struct PacketPageRequest {
79    pub command: u16,
80    pub flags: u16,
81    pub reserved0: u32,
82    pub offset: u64,
83    pub length: u64,
84    pub reserved1: u64,
85}
86
87#[repr(C)]
88#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
89pub struct PacketProcessorPowerLevelTransitionRequest {
90    /// Request targeting the provided power domain.
91    pub domain_id: u32,
92    pub options: u32,
93    pub control_argument: u64,
94    pub control_interface: u64,
95    pub reserved: u64,
96}
97
98#[repr(C)]
99#[derive(Clone, Copy, Debug, Eq, PartialEq)]
100pub struct PortPacket {
101    pub key: u64,
102    pub r#type: u32,
103    pub status: Status,
104    pub signal: PacketSignal,
105    pub exception: PacketException,
106    pub guest_bell: PacketGuestBell,
107    pub guest_mem: PacketGuestMem,
108    pub guest_io: PacketGuestIo,
109    pub guest_vcpu: PacketGuestVcpu,
110    pub interrupt: PacketInterrupt,
111    pub page_request: PacketPageRequest,
112    pub processor_power_level_transition: PacketProcessorPowerLevelTransitionRequest,
113}
fidl_data_zx/port.rs

fidl_data_zx/
port.rs
