fidl_data_zx/
pci.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zx` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use zerocopy::{FromBytes, IntoBytes};
11
12use crate::zx_common::*;
13
14#[repr(C)]
15#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
16pub struct PciBar {
17    pub id: u32,
18    pub r#type: u32,
19    pub size: usize,
20}
21
22#[repr(C)]
23#[derive(Clone, Copy, Debug, Eq, PartialEq)]
24pub struct PcieDeviceInfo {
25    pub vendor_id: u16,
26    pub device_id: u16,
27    pub base_class: u8,
28    pub sub_class: u8,
29    pub program_interface: u8,
30    pub revision_id: u8,
31    pub bus_id: u8,
32    pub dev_id: u8,
33    pub func_id: u8,
34}
35
36#[repr(C)]
37#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
38pub struct PciInitArg {
39    pub num_irqs: u32,
40    pub addr_window_count: u32,
41}
fidl_data_zx/pci.rs

fidl_data_zx/
pci.rs
