struct
Defined at line 71 of file ../../src/devices/pwm/drivers/aml-pwm/aml-pwm-regs.h
NOTE: TimeReg channel bit allocations are asymmetrical in Amlogic
hardware compared to DeltaSigmaReg.
Channel A timers (a1 / a2) occupy the upper 16 bits [31:16] ([31:24] and [23:16]).
Channel B timers (b1 / b2) occupy the lower 16 bits [15:0] ([15:8] and [7:0]).
Do NOT swap them to match DeltaSigmaReg (where a is [15:0] and b is [31:16]).
Public Members
Field field