class Status0AReg
Defined at line 753 of file ../../src/devices/power/drivers/fusb302/registers.h
STATUS0A - Additional configuration for automated power role detection.
This register has reserved/undocumented bits. It can only be safely updated
via read/modify/write operations.
This is a read-only register.
Rev 5 datasheet: Table 31 on page 24
Public Members
field_softfail_766 field_retryfail_776 field_power3_782 field_power2_788 field_softrst_793 field_hardrst_798Public Methods
template <, >SelfType & set_softfail (typename SelfType::ValueType val)If true, the PD Protocol Layer signaled that a Soft Reset was not received.
The hardware implements usbpd3.1 6.6.1 "CRCReceiveTimer" and 6.7.2 "Retry
Counter". This bit signals that the retry counter has reached the
nRetryCount limit set by `n_retries` in `Control3Reg`
after sending a a Soft Reset message.
This bit is cleared when the BMC PHY is asked to start a transmission via
the `tx_start` bit in `Control0Reg` or via the TXON token, and
when the BMC PHY is asked to send a Hard Reset message via the
`send_hard_reset` bit in the `Control3Reg` register.
Defined at line 766 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType softfail ()If true, the PD Protocol Layer signaled that a Soft Reset was not received.
The hardware implements usbpd3.1 6.6.1 "CRCReceiveTimer" and 6.7.2 "Retry
Counter". This bit signals that the retry counter has reached the
nRetryCount limit set by `n_retries` in `Control3Reg`
after sending a a Soft Reset message.
This bit is cleared when the BMC PHY is asked to start a transmission via
the `tx_start` bit in `Control0Reg` or via the TXON token, and
when the BMC PHY is asked to send a Hard Reset message via the
`send_hard_reset` bit in the `Control3Reg` register.
Defined at line 766 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType retryfail ()If true, the PD Protocol Layer signaled that a message was not received.
The hardware implements usbpd3.1 6.6.1 "CRCReceiveTimer" and 6.7.2 "Retry
Counter". This bit signals that the retry counter has reached the
nRetryCount limit set by `n_retries` in `Control3Reg`
after sending a non-Reset message.
This bit is cleared under the same conditions as `softfail`.
Defined at line 776 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >SelfType & set_retryfail (typename SelfType::ValueType val)If true, the PD Protocol Layer signaled that a message was not received.
The hardware implements usbpd3.1 6.6.1 "CRCReceiveTimer" and 6.7.2 "Retry
Counter". This bit signals that the retry counter has reached the
nRetryCount limit set by `n_retries` in `Control3Reg`
after sending a non-Reset message.
This bit is cleared under the same conditions as `softfail`.
Defined at line 776 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType power3 ()If true, the hardware is forcing PWR[3] (power gate 3) to be enabled.
This is a hardware override for the `pwr3` bit in the
`PowerReg` register.
Defined at line 782 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >SelfType & set_power3 (typename SelfType::ValueType val)If true, the hardware is forcing PWR[3] (power gate 3) to be enabled.
This is a hardware override for the `pwr3` bit in the
`PowerReg` register.
Defined at line 782 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType power2 ()If true, the hardware is forcing PWR[2] (power gate 2) to be enabled.
This is a hardware override for the `pwr2` bit in the
`PowerReg` register.
Defined at line 788 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >SelfType & set_power2 (typename SelfType::ValueType val)If true, the hardware is forcing PWR[2] (power gate 2) to be enabled.
This is a hardware override for the `pwr2` bit in the
`PowerReg` register.
Defined at line 788 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >SelfType & set_softrst (typename SelfType::ValueType val)If true, the receiver in the BMC PHY decoded a Soft Reset message.
The Rev 5 datasheet does not specify when this bit gets reset.
Defined at line 793 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType softrst ()If true, the receiver in the BMC PHY decoded a Soft Reset message.
The Rev 5 datasheet does not specify when this bit gets reset.
Defined at line 793 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >typename SelfType::ValueType hardrst ()If true, the receiver in the BMC PHY decoded a Hard Reset ordered set.
The Rev 5 datasheet does not specify when this bit gets reset.
Defined at line 798 of file ../../src/devices/power/drivers/fusb302/registers.h
template <, >SelfType & set_hardrst (typename SelfType::ValueType val)If true, the receiver in the BMC PHY decoded a Hard Reset ordered set.
The Rev 5 datasheet does not specify when this bit gets reset.
Defined at line 798 of file ../../src/devices/power/drivers/fusb302/registers.h
hwreg::I2cRegisterAddr<Status0AReg> Get ()Defined at line 800 of file ../../src/devices/power/drivers/fusb302/registers.h