class NodeSetDebugTimeoutLogDeadlineRequest
Defined at line 2051 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
Public Methods
bool IsEmpty ()
Returns whether no field is set.
bool HasUnknownData ()
Returns whether the table references unknown fields.
::fidl::WireTableBuilder< ::fuchsia_sysmem2::wire::NodeSetDebugTimeoutLogDeadlineRequest> Builder (::fidl::AnyArena & arena)
Return a builder that by defaults allocates of an arena.
::fidl::WireTableExternalBuilder< ::fuchsia_sysmem2::wire::NodeSetDebugTimeoutLogDeadlineRequest> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::NodeSetDebugTimeoutLogDeadlineRequest>> frame)
Return a builder that relies on explicitly allocating |fidl::ObjectView|s.
void NodeSetDebugTimeoutLogDeadlineRequest ()
Defined at line 2053 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
void NodeSetDebugTimeoutLogDeadlineRequest (const NodeSetDebugTimeoutLogDeadlineRequest & other)
Defined at line 2054 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
NodeSetDebugTimeoutLogDeadlineRequest & operator= (const NodeSetDebugTimeoutLogDeadlineRequest & other)
Defined at line 2055 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
void NodeSetDebugTimeoutLogDeadlineRequest (NodeSetDebugTimeoutLogDeadlineRequest && other)
Defined at line 2056 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
int64_t & deadline ()
bool has_deadline ()
NodeSetDebugTimeoutLogDeadlineRequest & operator= (NodeSetDebugTimeoutLogDeadlineRequest && other)
Defined at line 2057 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
NodeSetDebugTimeoutLogDeadlineRequest & set_deadline (::fidl::ObjectView<int64_t> elem)
NodeSetDebugTimeoutLogDeadlineRequest & set_deadline (std::nullptr_t )
NodeSetDebugTimeoutLogDeadlineRequest & clear_deadline ()
void NodeSetDebugTimeoutLogDeadlineRequest (::fidl::AnyArena & allocator)
void NodeSetDebugTimeoutLogDeadlineRequest (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::NodeSetDebugTimeoutLogDeadlineRequest>> && frame)
This constructor allows a user controlled allocation (not using a Arena).
It should only be used when performance is key.
As soon as the frame is given to the table, it must not be used directly or for another table.
void Allocate (::fidl::AnyArena & allocator)
void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::NodeSetDebugTimeoutLogDeadlineRequest>> && frame_ptr)
void ~NodeSetDebugTimeoutLogDeadlineRequest ()
Defined at line 2059 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h
Friends
class WireTableBaseBuilder
class WireTableBaseBuilder