class BufferMemorySettings

Defined at line 8598 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

These are memory-related settings for all buffers of a buffer collection.

Public Methods

void BufferMemorySettings ()

Defined at line 8600 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void BufferMemorySettings (const BufferMemorySettings & other)

Defined at line 8601 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

bool has_heap ()

BufferMemorySettings & operator= (const BufferMemorySettings & other)

Defined at line 8602 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void BufferMemorySettings (BufferMemorySettings && other)

Defined at line 8603 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_sysmem2::wire::BufferMemorySettings> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_sysmem2::wire::BufferMemorySettings> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferMemorySettings>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

BufferMemorySettings & operator= (BufferMemorySettings && other)

Defined at line 8604 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

uint64_t & size_bytes ()

This field will always be set by sysmem.

Rule for producers: For `BufferCollectionInfo` with

`ImageFormatConstraints`, storing an image of a given `ImageFormat` in a

buffer of that `BufferCollection` is only allowed if the result of

calling `ImageFormatImageSize` or a strictly equivalent computation is

less than or equal to `size_bytes`.

Producer participants _must_ stay within `size_bytes` when determining

whether an image will fit in a buffer, even if the VMO's size is larger

than this.

Failure of a producer to use `size_bytes` as the constraint (not VMO

size) when determining whether a given `ImageFormat` will fit in a

buffer will, in general, cause problems for any participant that has set

ImageFormatConstraints.pad_for_block_size to larger than {1, 1}, or

pad_beyond_image_size_bytes to greater than 0. Those participants rely

on the ability to access bytes in the VMO beyond the image size. Putting

an image in the VMO that exceeds `size_bytes` can potentially lead to

those participants trying to access an offset beyond the last page of

the VMO.

Similarly, any future padding-only constraint which is irrelevant to a

non-padding participant when locating each valid pixel's valid data will

also be accounted for by checking `ImageFormatImageSize()` against

`size_bytes` instead of the VMO size.

Following this rule allows producers to not need to worry about

arbitrary padding requirements of participants, including future-added

padding-only constraints.

The `bytes_per_row` and rounding up to a tile size boundary are included

in `ImageFormatImageSize` and accounted for in `size_bytes`, even though

these two aspects are partially about padding. These two aspects are

included in the `ImageFormatImageSize` calculation because these two

aspects are also relevant to all participants that need to locate pixel

data. The `fuchsia.images2.ImageFormat` intentionally doesn't contain

any padding-only fields.

Participants with a padding constraint (in addition to `bytes_per_row`

or tile size boundary), such as pad_for_block_size or

pad_beyond_image_size_bytes, are allowed to access, but not treat as

meaningful, bytes which are at offset `size_bytes` up to the max offset

implied by their own padding constraint, which will never exceed the VMO

size minus 1, as long as the `ImageFormatImageSize` is less than or

equal to `BufferMemorySettings.size_bytes` and other constraints under

`BufferCollectionInfo` aren't violated by the producer.

The same `size_bytes` value is sent to all participants.

This field is not page aligned. This value rounded up to

zx_system_page_size() boundary is guaranteed to be less than or equal

the buffer VMO size. In other words, the VMO can have more pages than

implied by this value, due to padding-only constraints from

participant(s).

bool has_size_bytes ()

bool & is_physically_contiguous ()

This field will always be set by sysmem.

bool has_is_physically_contiguous ()

bool & is_secure ()

This field will always be set by sysmem.

bool has_is_secure ()

::fuchsia_sysmem2::wire::CoherencyDomain & coherency_domain ()

This field will always be set by sysmem.

bool has_coherency_domain ()

::fuchsia_sysmem2::wire::Heap & heap ()

The specific heap from which buffers are allocated.

This field will always be set by sysmem.

uint64_t & raw_vmo_size ()

This is guaranteed to be equal to the VMO size obtained via

`zx_vmo_get_size`. This field is here because `pad_*` constraints can

result in the VMO size being larger than implied by `size_bytes`, and

for participants using `pad_*` constraints, it can be convenient to have

this field available rather than having to query for the VMO size.

When checking with `ImageFormatImageSize` to see if an image will fit in

a buffer, use `size_bytes` as the threshold, not `raw_vmo_size`.

Producers using `pad_*` constraints must still only put images in the

buffer which have `ImageFormatImageSize()

= size_bytes`. Participants

using `pad_*` constraints are allowed to access bytes beyond

`size_bytes` consistent with what the participant set for the pad_*

constriant(s), which will always fit within `raw_vmo_size` assuming

correct operation of the participant and sysmem. This field can be

useful for double-checking that accesses will be within the VMO.

When setting up VMO mappings and VMO pins, a participant using `pad_*`

constraint(s) should use `raw_vmo_size` for the size of the mapping. In

contrast, a participant not using any pad_* constraint can use

`size_bytes` rounded up to a page size boundary or said participant can

use raw_vmo_size, but for that participant, using `size_bytes` rounded

up to the page size can avoid mapping a few pages.

bool has_raw_vmo_size ()

BufferMemorySettings & set_size_bytes (::fidl::ObjectView<uint64_t> elem)

BufferMemorySettings & set_size_bytes (std::nullptr_t )

BufferMemorySettings & clear_size_bytes ()

BufferMemorySettings & set_is_physically_contiguous (bool elem)

BufferMemorySettings & clear_is_physically_contiguous ()

BufferMemorySettings & set_is_secure (bool elem)

BufferMemorySettings & clear_is_secure ()

BufferMemorySettings & set_coherency_domain (::fuchsia_sysmem2::wire::CoherencyDomain elem)

BufferMemorySettings & clear_coherency_domain ()

BufferMemorySettings & set_heap (::fidl::ObjectView< ::fuchsia_sysmem2::wire::Heap> elem)

BufferMemorySettings & set_heap (std::nullptr_t )

BufferMemorySettings & clear_heap ()

BufferMemorySettings & set_raw_vmo_size (::fidl::ObjectView<uint64_t> elem)

BufferMemorySettings & set_raw_vmo_size (std::nullptr_t )

BufferMemorySettings & clear_raw_vmo_size ()

void BufferMemorySettings (::fidl::AnyArena & allocator)

void BufferMemorySettings (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferMemorySettings>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferMemorySettings>> && frame_ptr)

void ~BufferMemorySettings ()

Defined at line 8606 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder