class FormatCostEntry

Defined at line 13565 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

A FormatCostEntry can be used to influence which PixelFormatAndModifier is

chosen for a buffer collection, optionally taking BufferUsage into account.

The default cost is f32::MAX, so any specified cost with a non-MAX value

will prefer the specified format over any formats that don't have any

FormatCost entry.

Entries which have the same pixel_format, pixel_format_modifier, and

required_usage_bits as a previous entry will override that previous entry.

For matching purposes, an absent pixel_format_modifier matches LINEAR, and

an absent required_buffer_usage_bits matches all-0 usage bits.

Board info sysmem_defaults entries are logically before platform sysmem

entries.

Sysmem uses the resulting aggregated list of FormatCostEntry(s) when

breaking ties among the set of formats which are supported by all

participants of a buffer collection. For each mutually-supported format,

entries with non-matching format are ignored, and entries with extra

buffer_usage_bits set are ignored. Among the remaining entries, the entry

with the most usage bits in common with the aggregated participant usages is

selected to determine the cost (if a tie, the later entry wins). Then the

format with the lowest cost is chosen. If it's still a tie (equal cost), the

tie is broken arbitrarily but not randomly.

This is not intended as a mechanism to disallow selection of a format that

is supported by all participants of a buffer collection. If a participant

claims support for a format but fails to handle that format correctly, it

should be fixed to handle that format correctly or changed to stop claiming

support for that format.

This mechanism is intended to influence format selection toward more

efficient formats with better performance, lower memory bandwidth usage,

etc, for a given set of usage bits, taking into account quirks that may be

unique to a given board or overall platform config.

Public Methods

void FormatCostEntry ()

Defined at line 13567 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void FormatCostEntry (const FormatCostEntry & other)

Defined at line 13568 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

FormatCostEntry & operator= (const FormatCostEntry & other)

Defined at line 13569 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void FormatCostEntry (FormatCostEntry && other)

Defined at line 13570 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_sysmem2::wire::FormatCostEntry> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_sysmem2::wire::FormatCostEntry> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::FormatCostEntry>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

::fuchsia_sysmem2::wire::FormatCostKey & key ()

Must be set. If two entries have logically equal key (after field

defaults are applied), the later entry will override the earlier entry.

bool has_key ()

float & cost ()

Must be set. Lower costs win, but see also FormatCostKey fields re.

filtering entries by format and usage bits first.

When two entries (each with format supported by all the participants of

a buffer collection) have different costs, the lower cost entry (and its

format) is chosen.

For non-test scenarios, only use cost values > 0.0 (typically at least

1.0 as of this comment), with 0.0 and negative values reserved for

testing.

bool has_cost ()

FormatCostEntry & operator= (FormatCostEntry && other)

Defined at line 13571 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

FormatCostEntry & set_key (::fidl::ObjectView< ::fuchsia_sysmem2::wire::FormatCostKey> elem)

FormatCostEntry & set_key (std::nullptr_t )

FormatCostEntry & clear_key ()

FormatCostEntry & set_cost (float elem)

FormatCostEntry & clear_cost ()

void FormatCostEntry (::fidl::AnyArena & allocator)

void FormatCostEntry (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::FormatCostEntry>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::FormatCostEntry>> && frame_ptr)

void ~FormatCostEntry ()

Defined at line 13573 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder