class BufferUsage

Defined at line 13174 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

Describes how a client will access the contents of a buffer.

Public Methods

void BufferUsage ()

Defined at line 13176 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void BufferUsage (const BufferUsage & other)

Defined at line 13177 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_sysmem2::wire::BufferUsage> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_sysmem2::wire::BufferUsage> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferUsage>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

uint32_t & none ()

If the client sets this field, the client should not set any other

fields in the same table instance. The only valid bit in this field is

`NONE_USAGE` which must be set if this field is set. The point of this

field and the one bit set in this field is to essentially prove that the

client really means they aren't going to use the buffers, so don't need

any VMOs (didn't just fail to fill out the table).

bool has_none ()

uint32_t & cpu ()

If set, holds CPU usage bits. See `CPU_USAGE_*` flags in usages.fidl.

bool has_cpu ()

bool has_display ()

BufferUsage & operator= (const BufferUsage & other)

Defined at line 13178 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

void BufferUsage (BufferUsage && other)

Defined at line 13179 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

BufferUsage & operator= (BufferUsage && other)

Defined at line 13180 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

uint32_t & vulkan ()

If set, holds vulkan usage bits. See `VULKAN_IMAGE_*` and

`VULKAN_BUFFER_*` bits in usages.fidl. The `VULKAN_USAGE_*` bit

definitions/names are deprecated.

bool has_vulkan ()

uint32_t & display ()

If set, holds display usage bits. See `DISPLAY_USAGE_*` bits in

usages.fidl.

uint32_t & video ()

If set, holds video usage bits. See `VIDEO_USAGE_*` bits in usages.fidl.

bool has_video ()

BufferUsage & set_none (uint32_t elem)

BufferUsage & clear_none ()

BufferUsage & set_cpu (uint32_t elem)

BufferUsage & clear_cpu ()

BufferUsage & set_vulkan (uint32_t elem)

BufferUsage & clear_vulkan ()

BufferUsage & set_display (uint32_t elem)

BufferUsage & clear_display ()

BufferUsage & set_video (uint32_t elem)

BufferUsage & clear_video ()

void BufferUsage (::fidl::AnyArena & allocator)

void BufferUsage (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferUsage>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_sysmem2::wire::BufferUsage>> && frame_ptr)

void ~BufferUsage ()

Defined at line 13182 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/cpp/fidl/fuchsia.sysmem2/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder