class SamplerSetProcessInfoRequest

Defined at line 1253 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_memory_sampler::wire::SamplerSetProcessInfoRequest> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_memory_sampler::wire::SamplerSetProcessInfoRequest> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_memory_sampler::wire::SamplerSetProcessInfoRequest>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void SamplerSetProcessInfoRequest ()

Defined at line 1255 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

void SamplerSetProcessInfoRequest (const SamplerSetProcessInfoRequest & other)

Defined at line 1256 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

SamplerSetProcessInfoRequest & operator= (const SamplerSetProcessInfoRequest & other)

Defined at line 1257 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

void SamplerSetProcessInfoRequest (SamplerSetProcessInfoRequest && other)

Defined at line 1258 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

SamplerSetProcessInfoRequest & operator= (SamplerSetProcessInfoRequest && other)

Defined at line 1259 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

::fidl::StringView & process_name ()

Name of the instrumented process.

bool has_process_name ()

::fidl::VectorView< ::fuchsia_memory_sampler::wire::ModuleMap> & module_map ()

Current module layout, for symbolization.

bool has_module_map ()

void ~SamplerSetProcessInfoRequest ()

Defined at line 1261 of file fidling/gen/sdk/fidl/fuchsia.memory.sampler/fuchsia.memory.sampler/cpp/fidl/fuchsia.memory.sampler/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder