class VregSetStateRequest

Defined at line 387 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_vreg::wire::VregSetStateRequest> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_vreg::wire::VregSetStateRequest> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregSetStateRequest>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregSetStateRequest>> && frame_ptr)

void VregSetStateRequest ()

Defined at line 389 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

void VregSetStateRequest (VregSetStateRequest && other)

Defined at line 392 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

VregSetStateRequest & operator= (VregSetStateRequest && other)

Defined at line 393 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

uint32_t & step ()

bool has_step ()

bool & enable ()

bool has_enable ()

uint32_t & current_ua ()

::fuchsia_hardware_vreg::wire::RegulatorMode & mode ()

bool has_mode ()

VregSetStateRequest & operator= (const VregSetStateRequest & other)

Defined at line 391 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

VregSetStateRequest & set_step (uint32_t elem)

VregSetStateRequest & clear_step ()

VregSetStateRequest & set_enable (bool elem)

VregSetStateRequest & clear_enable ()

VregSetStateRequest & set_current_ua (uint32_t elem)

VregSetStateRequest & clear_current_ua ()

VregSetStateRequest & set_mode (::fuchsia_hardware_vreg::wire::RegulatorMode elem)

VregSetStateRequest & clear_mode ()

void VregSetStateRequest (::fidl::AnyArena & allocator)

void VregSetStateRequest (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregSetStateRequest>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void VregSetStateRequest (const VregSetStateRequest & other)

Defined at line 390 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

bool has_current_ua ()

void ~VregSetStateRequest ()

Defined at line 395 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder