class VregMetadata

Defined at line 125 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

Public Members

static const char[] kSerializableName

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_vreg::wire::VregMetadata> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_vreg::wire::VregMetadata> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregMetadata>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregMetadata>> && frame_ptr)

void VregMetadata ()

Defined at line 128 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

void VregMetadata (const VregMetadata & other)

Defined at line 129 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

void VregMetadata (VregMetadata && other)

Defined at line 131 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

::fidl::StringView & name ()

Voltage regulator name. This will be set as fuchsia.regulator.NAME property on the child

device to which regulator consumers can bind to.

bool has_name ()

uint32_t & min_voltage_uv ()

Minimum voltage of voltage regulator in microvolts.

bool has_min_voltage_uv ()

VregMetadata & operator= (const VregMetadata & other)

Defined at line 130 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

VregMetadata & operator= (VregMetadata && other)

Defined at line 132 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

uint32_t & voltage_step_uv ()

Size of a voltage step in microvolts.

bool has_voltage_step_uv ()

uint32_t & num_steps ()

Number of voltage steps. For example, voltage regulator with voltage range 400 uV- 1000 uV

inclusive and step size 20 uV. Total number of steps is (1000 uV - 400 uV) / 20 uV + 1 = 31

steps.

bool has_num_steps ()

VregMetadata & set_name (::fidl::ObjectView< ::fidl::StringView> elem)

VregMetadata & set_name (std::nullptr_t )

VregMetadata & clear_name ()

VregMetadata & set_min_voltage_uv (uint32_t elem)

VregMetadata & clear_min_voltage_uv ()

VregMetadata & set_voltage_step_uv (uint32_t elem)

VregMetadata & clear_voltage_step_uv ()

VregMetadata & set_num_steps (uint32_t elem)

VregMetadata & clear_num_steps ()

void VregMetadata (::fidl::AnyArena & allocator)

void VregMetadata (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_vreg::wire::VregMetadata>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void ~VregMetadata ()

Defined at line 134 of file fidling/gen/sdk/fidl/fuchsia.hardware.vreg/fuchsia.hardware.vreg/cpp/fidl/fuchsia.hardware.vreg/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder