class SpiChannel

Defined at line 76 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

Represents a single device on a SPI bus.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_spi_businfo::wire::SpiChannel> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_spi_businfo::wire::SpiChannel> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_spi_businfo::wire::SpiChannel>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_spi_businfo::wire::SpiChannel>> && frame_ptr)

void SpiChannel ()

Defined at line 78 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

void SpiChannel (const SpiChannel & other)

Defined at line 79 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

void SpiChannel (SpiChannel && other)

Defined at line 81 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

uint32_t & cs ()

Chip select number for the device.

bool has_cs ()

SpiChannel & operator= (SpiChannel && other)

Defined at line 82 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

uint32_t & vid ()

Vendor ID. Used when binding via platform bus device IDs.

bool has_vid ()

uint32_t & pid ()

Product ID. Used when binding via platform bus device IDs.

bool has_pid ()

uint32_t & did ()

Device ID. Used when binding via platform bus device IDs.

bool has_did ()

bool & cs_polarity_high ()

Chip select polarity: true == high, false == low.

bool has_cs_polarity_high ()

uint8_t & word_length_bits ()

Size in bits of a single word on the SPI bus.

bool has_word_length_bits ()

bool & is_bus_controller ()

Are we in charge of the bus?

bool has_is_bus_controller ()

bool & clock_polarity_high ()

Clock polarity. true == high, false == low.

bool has_clock_polarity_high ()

::fuchsia_hardware_spi_businfo::wire::SpiClockPhase & clock_phase ()

Clock phase.

bool has_clock_phase ()

SpiChannel & operator= (const SpiChannel & other)

Defined at line 80 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

SpiChannel & set_cs (uint32_t elem)

SpiChannel & clear_cs ()

SpiChannel & set_vid (uint32_t elem)

SpiChannel & clear_vid ()

SpiChannel & set_pid (uint32_t elem)

SpiChannel & clear_pid ()

SpiChannel & set_did (uint32_t elem)

SpiChannel & clear_did ()

SpiChannel & set_cs_polarity_high (bool elem)

SpiChannel & clear_cs_polarity_high ()

SpiChannel & set_word_length_bits (uint8_t elem)

SpiChannel & clear_word_length_bits ()

SpiChannel & set_is_bus_controller (bool elem)

SpiChannel & clear_is_bus_controller ()

SpiChannel & set_clock_polarity_high (bool elem)

SpiChannel & clear_clock_polarity_high ()

SpiChannel & set_clock_phase (::fuchsia_hardware_spi_businfo::wire::SpiClockPhase elem)

SpiChannel & clear_clock_phase ()

void SpiChannel (::fidl::AnyArena & allocator)

void SpiChannel (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_spi_businfo::wire::SpiChannel>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void ~SpiChannel ()

Defined at line 84 of file fidling/gen/sdk/fidl/fuchsia.hardware.spi.businfo/fuchsia.hardware.spi.businfo/cpp/fidl/fuchsia.hardware.spi.businfo/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder