class BusReadBarResult
Defined at line 528 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
Public Methods
void BusReadBarResult ()void BusReadBarResult (const BusReadBarResult & )Defined at line 534 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
BusReadBarResult & operator= (const BusReadBarResult & )Defined at line 535 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
void BusReadBarResult (BusReadBarResult && )Defined at line 536 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
bool has_invalid_tag ()bool is_response ()BusReadBarResult WithResponse (::fidl::ObjectView< ::fuchsia_hardware_pci::wire::BusReadBarResponse> val)BusReadBarResult & operator= (BusReadBarResult && )Defined at line 537 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
template <typename... Args>BusReadBarResult WithResponse (::fidl::AnyArena & allocator, Args &&... args)Defined at line 551 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h
::fuchsia_hardware_pci::wire::BusReadBarResponse & response ()const ::fuchsia_hardware_pci::wire::BusReadBarResponse & response ()bool is_err ()BusReadBarResult WithErr (int32_t val)int32_t & err ()const int32_t & err ()::fuchsia_hardware_pci::wire::BusReadBarResult::Tag Which ()Enumerations
enum Tag| Name | Value |
|---|---|
| kResponse | 1 |
| kErr | 2 |
Defined at line 539 of file fidling/gen/sdk/fidl/fuchsia.hardware.pci/fuchsia.hardware.pci/cpp/fidl/fuchsia.hardware.pci/cpp/wire_types.h