class PortInfo

Defined at line 1600 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Logical port information.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_network::wire::PortInfo> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_network::wire::PortInfo> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortInfo>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void PortInfo ()

Defined at line 1602 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

void PortInfo (const PortInfo & other)

Defined at line 1603 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

PortInfo & operator= (const PortInfo & other)

Defined at line 1604 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

void PortInfo (PortInfo && other)

Defined at line 1605 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

::fuchsia_hardware_network::wire::PortId & id ()

Port's identifier. Required.

bool has_id ()

::fuchsia_hardware_network::wire::PortBaseInfo & base_info ()

bool has_base_info ()

PortInfo & operator= (PortInfo && other)

Defined at line 1606 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

PortInfo & set_id (::fuchsia_hardware_network::wire::PortId elem)

PortInfo & clear_id ()

PortInfo & set_base_info (::fidl::ObjectView< ::fuchsia_hardware_network::wire::PortBaseInfo> elem)

PortInfo & set_base_info (std::nullptr_t )

PortInfo & clear_base_info ()

void PortInfo (::fidl::AnyArena & allocator)

void PortInfo (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortInfo>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortInfo>> && frame_ptr)

void ~PortInfo ()

Defined at line 1608 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder