class PortBaseInfo

class PortBaseInfo

Defined at line 1306 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Port base info.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_network::wire::PortBaseInfo> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_network::wire::PortBaseInfo> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortBaseInfo>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)
void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortBaseInfo>> && frame_ptr)
void PortBaseInfo ()

Defined at line 1308 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

void PortBaseInfo (PortBaseInfo && other)

Defined at line 1311 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

PortBaseInfo & operator= (PortBaseInfo && other)

Defined at line 1312 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

::fuchsia_hardware_network::wire::PortClass & port_class ()

Port's class. Required.

bool has_port_class ()
::fidl::VectorView< ::fuchsia_hardware_network::wire::FrameType> & rx_types ()

Supported rx frame types on this port. Required.

Clients may open sessions subscribing to a subset of `rx_types` frame

types on this port.

bool has_rx_types ()
bool has_tx_types ()
PortBaseInfo & operator= (const PortBaseInfo & other)

Defined at line 1310 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

PortBaseInfo & set_port_class (::fuchsia_hardware_network::wire::PortClass elem)
PortBaseInfo & clear_port_class ()
PortBaseInfo & set_rx_types (::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_network::wire::FrameType>> elem)
PortBaseInfo & set_rx_types (std::nullptr_t )
PortBaseInfo & clear_rx_types ()
PortBaseInfo & set_tx_types (::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_network::wire::FrameTypeSupport>> elem)
PortBaseInfo & set_tx_types (std::nullptr_t )
PortBaseInfo & clear_tx_types ()
void PortBaseInfo (::fidl::AnyArena & allocator)
void PortBaseInfo (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::PortBaseInfo>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void PortBaseInfo (const PortBaseInfo & other)

Defined at line 1309 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

::fidl::VectorView< ::fuchsia_hardware_network::wire::FrameTypeSupport> & tx_types ()

Supported tx frame types on this port. Required.

Frames destined to this port whose frame type is not in `tx_types` are

returned with an error.

Some network devices may need to perform partial frame parsing and

serialization and, for that reason, `tx_types` is a vector of

[`FrameTypeSupport`] which includes specific features per frame type.

For example, a device that supports Ethernet frames but needs to convert

the Ethernet header may only support standard Ethernet II frames, and

not any "raw" Ethernet frame.

void ~PortBaseInfo ()

Defined at line 1314 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Friends

class WireTableBaseBuilder
class WireTableBaseBuilder