class InitCall

class InitCall

Defined at line 1554 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

A fuchsia.hardware.clock.Clock call to make as part of an `InitStep`.

Public Methods

void InitCall ()
void InitCall (const InitCall & )

Defined at line 1558 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

void InitCall (InitCall && )

Defined at line 1560 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

bool IsUnknown ()

Defined at line 1571 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

template <typename... Args>
InitCall WithRateHz (::fidl::AnyArena & allocator, Args &&... args)

If set, the clock core driver will call `SetRate` with the given frequency in Hertz.

Defined at line 1606 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

template <typename... Args>
InitCall WithDelay (::fidl::AnyArena & allocator, Args &&... args)

If set, the clock core driver will delay for this long before processing the next step.

Defined at line 1635 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

bool has_invalid_tag ()
bool is_enable ()
InitCall WithEnable (::fuchsia_hardware_clockimpl::wire::EnableType val)

If set, the clock core driver will call `Enable`.

::fuchsia_hardware_clockimpl::wire::EnableType & enable ()

If set, the clock core driver will call `Enable`.

const ::fuchsia_hardware_clockimpl::wire::EnableType & enable ()

If set, the clock core driver will call `Enable`.

bool is_disable ()
InitCall WithDisable (::fuchsia_hardware_clockimpl::wire::DisableType val)

If set, the clock core driver will call `Disable`.

::fuchsia_hardware_clockimpl::wire::DisableType & disable ()

If set, the clock core driver will call `Disable`.

const ::fuchsia_hardware_clockimpl::wire::DisableType & disable ()

If set, the clock core driver will call `Disable`.

bool is_rate_hz ()
InitCall WithRateHz (::fidl::ObjectView<uint64_t> val)

If set, the clock core driver will call `SetRate` with the given frequency in Hertz.

InitCall & operator= (InitCall && )

Defined at line 1561 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

uint64_t & rate_hz ()

If set, the clock core driver will call `SetRate` with the given frequency in Hertz.

const uint64_t & rate_hz ()

If set, the clock core driver will call `SetRate` with the given frequency in Hertz.

bool is_input_idx ()
InitCall WithInputIdx (uint32_t val)

If set, the clock core driver will call `SetInput` with the given input index.

uint32_t & input_idx ()

If set, the clock core driver will call `SetInput` with the given input index.

const uint32_t & input_idx ()

If set, the clock core driver will call `SetInput` with the given input index.

bool is_delay ()
InitCall WithDelay (::fidl::ObjectView<int64_t> val)

If set, the clock core driver will delay for this long before processing the next step.

int64_t & delay ()

If set, the clock core driver will delay for this long before processing the next step.

const int64_t & delay ()

If set, the clock core driver will delay for this long before processing the next step.

::fuchsia_hardware_clockimpl::wire::InitCall::Tag Which ()
InitCall & operator= (const InitCall & )

Defined at line 1559 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h

Enumerations

enum Tag
Name Value
kEnable 1
kDisable 2
kRateHz 3
kInputIdx 4
kDelay 5
_do_not_handle_this__write_a_default_case_instead ::std::numeric_limits<::fidl_union_tag_t>::max()

Defined at line 1563 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/wire_types.h