class InitCall

Defined at line 1946 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/natural_types.h

A fuchsia.hardware.clock.Clock call to make as part of an `InitStep`.

Public Methods

void InitCall (InitCall && other)

InitCall & operator= (InitCall && other)

void InitCall (const InitCall & other)

InitCall & operator= (const InitCall & other)

bool operator== (const InitCall & other)

bool operator!= (const InitCall & other)

bool IsUnknown ()

::fuchsia_hardware_clockimpl::InitCall::Tag Which ()

InitCall WithEnable (::fuchsia_hardware_clockimpl::EnableType val)

const ::fidl::internal::UnionMemberView<1, Storage_> enable ()

::fidl::internal::UnionMemberView<1, Storage_> enable ()

InitCall & enable (::fuchsia_hardware_clockimpl::EnableType value)

If set, the clock core driver will call `Enable`.

InitCall WithDisable (::fuchsia_hardware_clockimpl::DisableType val)

const ::fidl::internal::UnionMemberView<2, Storage_> disable ()

::fidl::internal::UnionMemberView<2, Storage_> disable ()

InitCall & disable (::fuchsia_hardware_clockimpl::DisableType value)

If set, the clock core driver will call `Disable`.

InitCall WithRateHz (uint64_t val)

const ::fidl::internal::UnionMemberView<3, Storage_> rate_hz ()

::fidl::internal::UnionMemberView<3, Storage_> rate_hz ()

InitCall & rate_hz (uint64_t value)

If set, the clock core driver will call `SetRate` with the given frequency in Hertz.

InitCall WithInputIdx (uint32_t val)

const ::fidl::internal::UnionMemberView<4, Storage_> input_idx ()

::fidl::internal::UnionMemberView<4, Storage_> input_idx ()

InitCall & input_idx (uint32_t value)

If set, the clock core driver will call `SetInput` with the given input index.

InitCall WithDelay (int64_t val)

const ::fidl::internal::UnionMemberView<5, Storage_> delay ()

::fidl::internal::UnionMemberView<5, Storage_> delay ()

InitCall & delay (int64_t value)

If set, the clock core driver will delay for this long before processing the next step.

void InitCall (::fidl::internal::DefaultConstructPossiblyInvalidObjectTag )

Enumerations

enum Tag

Name	Value
kEnable	1
kDisable	2
kRateHz	3
kInputIdx	4
kDelay	5
_do_not_handle_this__write_a_default_case_instead	::std::numeric_limits<::fidl_union_tag_t>::max()

TODO: share union tag types between wire

natural.

Defined at line 1954 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/natural_types.h

Friends

class NaturalUnionCodingTraits