class PlugState

Defined at line 190 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Plug state for the interconnect.

If the driver reports a `plug_detect_capabilities` equal to HARDWIRED, then the driver should

respond to `WatchElementState` only the first time it is called for a given interconnect, with

`plugged` set to true and `plug_state_time` set to time '0'.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void PlugState ()

Defined at line 192 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void PlugState (const PlugState & other)

Defined at line 193 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

PlugState & operator= (const PlugState & other)

Defined at line 194 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void PlugState (PlugState && other)

Defined at line 195 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

PlugState & operator= (PlugState && other)

Defined at line 196 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

bool & plugged ()

Indicates whether the interconnect is currently plugged in.

Required

bool has_plugged ()

int64_t & plug_state_time ()

Indicates when the current `plugged` state was set, using `ZX_CLOCK_MONOTONIC`.

Cannot be negative.

Required.

bool has_plug_state_time ()

PlugState & set_plugged (bool elem)

PlugState & clear_plugged ()

PlugState & set_plug_state_time (::fidl::ObjectView<int64_t> elem)

PlugState & set_plug_state_time (std::nullptr_t )

PlugState & clear_plug_state_time ()

void PlugState (::fidl::AnyArena & allocator)

void PlugState (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState>> && frame_ptr)

void ~PlugState ()

Defined at line 198 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder