class Topology

Defined at line 3943 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

A `Topology` specifies how processing elements are arranged within the hardware.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::Topology> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::Topology> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::Topology>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::Topology>> && frame_ptr)

void Topology ()

Defined at line 3945 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void Topology (Topology && other)

Defined at line 3948 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

uint64_t & id ()

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

bool has_id ()

bool has_processing_elements_edge_pairs ()

Topology & operator= (const Topology & other)

Defined at line 3947 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Topology & operator= (Topology && other)

Defined at line 3949 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Topology & set_id (::fidl::ObjectView<uint64_t> elem)

Topology & set_id (std::nullptr_t )

Topology & clear_id ()

Topology & set_processing_elements_edge_pairs (::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::EdgePair>> elem)

Topology & set_processing_elements_edge_pairs (std::nullptr_t )

Topology & clear_processing_elements_edge_pairs ()

void Topology (::fidl::AnyArena & allocator)

void Topology (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::Topology>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Topology (const Topology & other)

Defined at line 3946 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::EdgePair> & processing_elements_edge_pairs ()

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type

DAI_INTERCONNECT or RING_BUFFER.

An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a

RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an

EdgeList entry as a `processing_element_id_from`, then within that Topology this same

element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and

vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

void ~Topology ()

Defined at line 3951 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder