class DaiInterconnectElementState

class DaiInterconnectElementState

Defined at line 562 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

State for an `Element` with `ElementType` `DAI_INTERCONNECT`.

Public Methods

void DaiInterconnectElementState ()

Defined at line 564 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void DaiInterconnectElementState (const DaiInterconnectElementState & other)

Defined at line 565 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void DaiInterconnectElementState (DaiInterconnectElementState && other)

Defined at line 567 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

::fuchsia_hardware_audio_signalprocessing::wire::PlugState & plug_state ()

The plug state for this DAI interconnect.

Required.

bool has_plug_state ()
int64_t & external_delay ()

The driver's best estimate of the external delay beyond this DAI endpoint, as the pipeline

is currently configured.

`external_delay` must be taken into account by the client when determining the requirements

for minimum lead time (during playback) and minimum capture delay (during capture).

If not included, `external_delay` is unknown; the client may treat it however it chooses

(e.g. consider it zero or some other duration, autodetect it, etc).

Optional. If specified, must be non-negative.

bool has_external_delay ()
DaiInterconnectElementState & operator= (const DaiInterconnectElementState & other)

Defined at line 566 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

DaiInterconnectElementState & operator= (DaiInterconnectElementState && other)

Defined at line 568 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

DaiInterconnectElementState & set_plug_state (::fidl::ObjectView< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState> elem)
DaiInterconnectElementState & set_plug_state (std::nullptr_t )
DaiInterconnectElementState & clear_plug_state ()
DaiInterconnectElementState & set_external_delay (::fidl::ObjectView<int64_t> elem)
DaiInterconnectElementState & set_external_delay (std::nullptr_t )
DaiInterconnectElementState & clear_external_delay ()
void DaiInterconnectElementState (::fidl::AnyArena & allocator)
void DaiInterconnectElementState (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)
void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnectElementState>> && frame_ptr)
void ~DaiInterconnectElementState ()

Defined at line 570 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Friends

class WireTableBaseBuilder
class WireTableBaseBuilder