class DaiInterconnect

Defined at line 404 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Parameters for an `Element` with `ElementType` `DAI_INTERCONNECT`.

Public Methods

void DaiInterconnect ()

Defined at line 406 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void DaiInterconnect (const DaiInterconnect & other)

Defined at line 407 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

DaiInterconnect & operator= (const DaiInterconnect & other)

Defined at line 408 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

void DaiInterconnect (DaiInterconnect && other)

Defined at line 409 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnect> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnect> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnect>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

DaiInterconnect & operator= (DaiInterconnect && other)

Defined at line 410 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

::fuchsia_hardware_audio_signalprocessing::wire::PlugDetectCapabilities & plug_detect_capabilities ()

Plug Detect Capabilities.

Required.

bool has_plug_detect_capabilities ()

DaiInterconnect & set_plug_detect_capabilities (::fuchsia_hardware_audio_signalprocessing::wire::PlugDetectCapabilities elem)

DaiInterconnect & clear_plug_detect_capabilities ()

void DaiInterconnect (::fidl::AnyArena & allocator)

void DaiInterconnect (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnect>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::DaiInterconnect>> && frame_ptr)

void ~DaiInterconnect ()

Defined at line 412 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder