class Topology

Defined at line 2013 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/natural_types.h

A `Topology` specifies how processing elements are arranged within the hardware.

Public Methods

void Topology (Storage_ storage)
void Topology ()

Defined at line 2018 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/natural_types.h

void Topology (Topology && )

Defined at line 2019 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/natural_types.h

void Topology (const Topology & other)
Topology & operator= (Topology && )

Defined at line 2020 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/natural_types.h

Topology & operator= (const Topology & other)
bool operator== (const Topology & other)
bool operator!= (const Topology & other)
bool IsEmpty ()
const std::optional<uint64_t> & id ()

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

::std::optional<uint64_t> & id ()

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

Topology & id (std::optional<uint64_t> value)

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

const std::optional< ::std::vector< ::fuchsia_hardware_audio_signalprocessing::EdgePair>> & processing_elements_edge_pairs ()

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type

DAI_INTERCONNECT or RING_BUFFER.

An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a

RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an

EdgeList entry as a `processing_element_id_from`, then within that Topology this same

element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and

vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

::std::optional< ::std::vector< ::fuchsia_hardware_audio_signalprocessing::EdgePair>> & processing_elements_edge_pairs ()

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type

DAI_INTERCONNECT or RING_BUFFER.

An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a

RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an

EdgeList entry as a `processing_element_id_from`, then within that Topology this same

element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and

vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

Topology & processing_elements_edge_pairs (std::optional< ::std::vector< ::fuchsia_hardware_audio_signalprocessing::EdgePair>> value)

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type

DAI_INTERCONNECT or RING_BUFFER.

An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a

RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an

EdgeList entry as a `processing_element_id_from`, then within that Topology this same

element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and

vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

void Topology (::fidl::internal::DefaultConstructPossiblyInvalidObjectTag )

Friends

class MemberVisitor
class NaturalTableCodingTraits