class StreamProperties

Defined at line 6754 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_audio::wire::StreamProperties> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_audio::wire::StreamProperties> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio::wire::StreamProperties>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio::wire::StreamProperties>> && frame_ptr)

void StreamProperties ()

Defined at line 6756 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

void StreamProperties (const StreamProperties & other)

Defined at line 6757 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

void StreamProperties (StreamProperties && other)

Defined at line 6759 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

::fidl::Array<uint8_t, 16> & unique_id ()

A unique identifier. If not included, there is no unique id for the StreamConfig.

`unique_id` arrays starting with 0x42, 0x54, ... (or `BT` in ASCII) are

reserved for drivers implementing Bluetooth technologies.

`unique_id` arrays starting with 0x55, 0x53, 0x42, ... (or `USB` in ASCII) are

reserved for drivers implementing USB technologies.

Note that even though the above values map to readable ASCII characters, array

values can span the entire uint8 range (0-255).

Optional.

bool has_unique_id ()

bool & is_input ()

Driver type is input (true) or output (false)

Required.

bool has_is_input ()

bool & can_mute ()

Gain mute capability. If not included, the StreamConfig can't mute.

Optional.

bool has_can_mute ()

bool & can_agc ()

Automatic Gain Control (AGC) capability. If not included, the StreamConfig can't AGC.

Optional.

bool has_can_agc ()

float & min_gain_db ()

Minimum gain in decibels.

Required.

bool has_min_gain_db ()

float & max_gain_db ()

Maximum gain in decibels.

Required.

bool has_max_gain_db ()

float & gain_step_db ()

Gain step in decibels, this value must not be negative, but may be zero to convey an

effectively continuous range of values. Must not exceed `max_gain_db` - `min_gain_db`.

Required.

bool has_gain_step_db ()

::fuchsia_hardware_audio::wire::PlugDetectCapabilities & plug_detect_capabilities ()

Plug Detect Capabilities.

Required.

bool has_plug_detect_capabilities ()

::fidl::StringView & manufacturer ()

UI string for the manufacturer name. If not included, the manufacturer is unspecified.

If included, this string must be non-empty.

Optional.

bool has_manufacturer ()

::fidl::StringView & product ()

UI string for the product name. If not included, the product name is unspecified.

If included, this string must be non-empty.

Optional.

bool has_product ()

uint32_t & clock_domain ()

An identifier for the clock domain in which this hardware operates. If

two hardware devices have the same clock domain, their clock rates are

identical and perfectly synchronized. Although these two clocks have the

same rate, the clock positions may be offset from each other by an

arbitrary (but fixed) amount. The clock_domain typically comes from a

system wide entity, such as a platform bus or global clock tree.

There are two special values:

* `CLOCK_DOMAIN_MONOTONIC` means the hardware is operating at the same

rate as the system montonic clock.

* `CLOCK_DOMAIN_EXTERNAL` means the hardware is operating at an unknown

rate and is not synchronized with any known clock, not even with

other clocks in domain `CLOCK_DOMAIN_EXTERNAL`.

If the domain is not `CLOCK_DOMAIN_MONOTONIC`, client must use position

notification updates to recover the hardware's clock.

Required.

bool has_clock_domain ()

StreamProperties & set_unique_id (::fidl::ObjectView< ::fidl::Array<uint8_t, 16>> elem)

StreamProperties & set_unique_id (std::nullptr_t )

StreamProperties & clear_unique_id ()

StreamProperties & operator= (StreamProperties && other)

Defined at line 6760 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

StreamProperties & set_is_input (bool elem)

StreamProperties & clear_is_input ()

StreamProperties & set_can_mute (bool elem)

StreamProperties & clear_can_mute ()

StreamProperties & set_can_agc (bool elem)

StreamProperties & clear_can_agc ()

StreamProperties & set_min_gain_db (float elem)

StreamProperties & clear_min_gain_db ()

StreamProperties & set_max_gain_db (float elem)

StreamProperties & clear_max_gain_db ()

StreamProperties & set_gain_step_db (float elem)

StreamProperties & clear_gain_step_db ()

StreamProperties & operator= (const StreamProperties & other)

Defined at line 6758 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

StreamProperties & set_plug_detect_capabilities (::fuchsia_hardware_audio::wire::PlugDetectCapabilities elem)

StreamProperties & clear_plug_detect_capabilities ()

StreamProperties & set_manufacturer (::fidl::ObjectView< ::fidl::StringView> elem)

StreamProperties & set_manufacturer (std::nullptr_t )

StreamProperties & clear_manufacturer ()

StreamProperties & set_product (::fidl::ObjectView< ::fidl::StringView> elem)

StreamProperties & set_product (std::nullptr_t )

StreamProperties & clear_product ()

StreamProperties & set_clock_domain (uint32_t elem)

StreamProperties & clear_clock_domain ()

void StreamProperties (::fidl::AnyArena & allocator)

void StreamProperties (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio::wire::StreamProperties>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void ~StreamProperties ()

Defined at line 6762 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio/fuchsia.hardware.audio/cpp/fidl/fuchsia.hardware.audio/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder