class SpiConfig

Defined at line 442 of file fidling/gen/sdk/fidl/fuchsia.hardware.amlogic.metadata/fuchsia.hardware.amlogic.metadata/cpp/fidl/fuchsia.hardware.amlogic.metadata/cpp/natural_types.h

Public Members

static const char[] kSerializableName

Public Methods

void SpiConfig (uint32_t bus_id, ::std::vector<uint32_t> cs, uint32_t clock_divider_register_value, bool use_enhanced_clock_mode, bool client_reverses_dma_transfers, uint32_t delay_control)

void SpiConfig ()

Default constructs a |SpiConfig| only if all of its members are default constructible.

Defined at line 454 of file fidling/gen/sdk/fidl/fuchsia.hardware.amlogic.metadata/fuchsia.hardware.amlogic.metadata/cpp/fidl/fuchsia.hardware.amlogic.metadata/cpp/natural_types.h

void SpiConfig (SpiConfig && )

Defined at line 457 of file fidling/gen/sdk/fidl/fuchsia.hardware.amlogic.metadata/fuchsia.hardware.amlogic.metadata/cpp/fidl/fuchsia.hardware.amlogic.metadata/cpp/natural_types.h

void SpiConfig (Storage_ storage)

void SpiConfig (const SpiConfig & other)

SpiConfig & operator= (const SpiConfig & other)

bool operator== (const SpiConfig & other)

bool operator!= (const SpiConfig & other)

uint32_t bus_id ()

uint32_t & bus_id ()

SpiConfig & bus_id (uint32_t value)

Setter for bus_id.

const ::std::vector<uint32_t> & cs ()

The index of the GPIO to use for each SPI device. GPIOs are expected to be fragments named

"gpio-cs-n", where n is the valued stored in `cs`.

Alternatively, entries may be set to `CS_CLIENT_MANAGED` to indicate that the client driver

will manage the cs GPIO for this chip (or that cs isn't needed).

::std::vector<uint32_t> & cs ()

The index of the GPIO to use for each SPI device. GPIOs are expected to be fragments named

"gpio-cs-n", where n is the valued stored in `cs`.

Alternatively, entries may be set to `CS_CLIENT_MANAGED` to indicate that the client driver

will manage the cs GPIO for this chip (or that cs isn't needed).

SpiConfig & cs (::std::vector<uint32_t> value)

The index of the GPIO to use for each SPI device. GPIOs are expected to be fragments named

"gpio-cs-n", where n is the valued stored in `cs`.

Alternatively, entries may be set to `CS_CLIENT_MANAGED` to indicate that the client driver

will manage the cs GPIO for this chip (or that cs isn't needed).

uint32_t clock_divider_register_value ()

The clock divider register value (NOT the actual clock divider) to use for SCLK.

If `use_enhanced_clock_mode` is true:

- `clock_divider_register_value` is written to ENHANCE_CNTL, and must be in [0, 255].

- The bus clock frequency is: core clock / (2 * (`clock_divider_register_value` + 1))

If `use_enhanced_clock_mode` is false:

- `clock_divider_register_value` is written to CONREG, and must be in [0, 7].

- The bus clock frequency is: core clock / (2 ^ (`clock_divider_register_value` + 2))

uint32_t & clock_divider_register_value ()

The clock divider register value (NOT the actual clock divider) to use for SCLK.

If `use_enhanced_clock_mode` is true:

- `clock_divider_register_value` is written to ENHANCE_CNTL, and must be in [0, 255].

- The bus clock frequency is: core clock / (2 * (`clock_divider_register_value` + 1))

If `use_enhanced_clock_mode` is false:

- `clock_divider_register_value` is written to CONREG, and must be in [0, 7].

- The bus clock frequency is: core clock / (2 ^ (`clock_divider_register_value` + 2))

SpiConfig & clock_divider_register_value (uint32_t value)

The clock divider register value (NOT the actual clock divider) to use for SCLK.

If `use_enhanced_clock_mode` is true:

- `clock_divider_register_value` is written to ENHANCE_CNTL, and must be in [0, 255].

- The bus clock frequency is: core clock / (2 * (`clock_divider_register_value` + 1))

If `use_enhanced_clock_mode` is false:

- `clock_divider_register_value` is written to CONREG, and must be in [0, 7].

- The bus clock frequency is: core clock / (2 ^ (`clock_divider_register_value` + 2))

SpiConfig & operator= (SpiConfig && )

Defined at line 458 of file fidling/gen/sdk/fidl/fuchsia.hardware.amlogic.metadata/fuchsia.hardware.amlogic.metadata/cpp/fidl/fuchsia.hardware.amlogic.metadata/cpp/natural_types.h

bool use_enhanced_clock_mode ()

If true, the SPI driver uses the enhanced clock mode instead of the regular clock mode.

bool & use_enhanced_clock_mode ()

If true, the SPI driver uses the enhanced clock mode instead of the regular clock mode.

SpiConfig & use_enhanced_clock_mode (bool value)

If true, the SPI driver uses the enhanced clock mode instead of the regular clock mode.

bool client_reverses_dma_transfers ()

If true, the client is responsible for reversing the endianness of transfers when using DMA.

bool & client_reverses_dma_transfers ()

If true, the client is responsible for reversing the endianness of transfers when using DMA.

SpiConfig & client_reverses_dma_transfers (bool value)

If true, the client is responsible for reversing the endianness of transfers when using DMA.

uint32_t delay_control ()

The value to use for the dlyctl field in TESTREG. The default value should work for

low-speed peripherals.

uint32_t & delay_control ()

The value to use for the dlyctl field in TESTREG. The default value should work for

low-speed peripherals.

SpiConfig & delay_control (uint32_t value)

The value to use for the dlyctl field in TESTREG. The default value should work for

low-speed peripherals.

void SpiConfig (::fidl::internal::DefaultConstructPossiblyInvalidObjectTag )

Friends

class MemberVisitor

class NaturalStructCodingTraits