class CoherencyDomain

Defined at line 107 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h

`INACCESSIBLE` is only for cases where there is no CPU access to the

buffers.

Device-local memory that isn't reachable from the CPU is `CoherencyDomain`

`INACCESSIBLE`, even if it's possible to cause a device (physical or

virtual) to copy the data from the `INACCESSIBLE` buffers to buffers that

are visible to the CPU. In other words, INACCESSIBLE does not imply secure,

but secure implies INACCESSIBLE.

`CPU` means producers must ensure that a consumer can read the produced data

with the CPU without the consumer needing to do additional cache ops not

already performed (as needed) by the producer.

`RAM` means producers must ensure that the produced data is entirely present

in RAM, without any dirty CPU cache lines, and a consumer must invalidate

(or flush and invalidate, typically) the CPU cache before reading data with

the CPU. The `RAM` domain can be faster than the `CPU` domain when all

access is via HW DMA, since in that case no CPU cache ops are required,

since no participant is actually reading/writing using the CPU.

Public Members

static CoherencyDomain CPU

static CoherencyDomain RAM

static CoherencyDomain INACCESSIBLE

void CoherencyDomain ()

Defined at line 109 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h

void CoherencyDomain (uint32_t value)

Defined at line 110 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h

uint32_t operator unsigned int ()

Defined at line 111 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h

bool IsUnknown ()

Defined at line 113 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h

CoherencyDomain Unknown ()

Defined at line 128 of file fidling/gen/sdk/fidl/fuchsia.sysmem2/fuchsia.sysmem2/hlcpp/fuchsia/sysmem2/cpp/fidl.h