class PortClass

Defined at line 561 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

The port class of an interface.

Public Members

static const fidl_type_t * FidlType

void PortClass ()

void PortClass (PortClass && )

PortClass WithLoopback (::fuchsia::net::interfaces::Empty && )

PortClass WithDevice (::fuchsia::hardware::network::PortClass && )

PortClass WithBlackhole (::fuchsia::net::interfaces::Empty && )

::std::unique_ptr<PortClass> New ()

void Encode (::fidl::Encoder * encoder, size_t offset, std::optional< ::fidl::HandleInformation> maybe_handle_info)

void Decode (::fidl::Decoder * _decoder, PortClass * value, size_t offset)

zx_status_t Clone (PortClass * result)

PortClass & SetUnknownData (fidl_xunion_tag_t ordinal, std::vector<uint8_t> bytes)

bool has_invalid_tag ()

Defined at line 591 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

bool is_loopback ()

Defined at line 595 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

::fuchsia::net::interfaces::Empty & loopback ()

The interface is loopback.

Defined at line 598 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

const ::fuchsia::net::interfaces::Empty & loopback ()

The interface is loopback.

Defined at line 604 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

bool is_device ()

Defined at line 610 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

::fuchsia::hardware::network::PortClass & device ()

The interface's network device port class.

Defined at line 613 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

const ::fuchsia::hardware::network::PortClass & device ()

The interface's network device port class.

Defined at line 619 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

bool is_blackhole ()

Defined at line 625 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

::fuchsia::net::interfaces::Empty & blackhole ()

The interface is a blackhole interface.

Defined at line 628 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

const ::fuchsia::net::interfaces::Empty & blackhole ()

The interface is a blackhole interface.

Defined at line 634 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

::fuchsia::net::interfaces::PortClass::Tag Which ()

Defined at line 641 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

fidl_xunion_tag_t Ordinal ()

You probably want to use Which() method instead of Ordinal(). Use Ordinal() only when you need

access to the raw integral ordinal value.

Defined at line 655 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

const std::vector<uint8_t> * UnknownBytes ()

Defined at line 658 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

void ~PortClass ()

PortClass & operator= (PortClass && )

PortClass & set_loopback (::fuchsia::net::interfaces::Empty value)

PortClass & set_device (::fuchsia::hardware::network::PortClass value)

PortClass & set_blackhole (::fuchsia::net::interfaces::Empty value)

enum Tag

Name	Value
kUnknown	0
kLoopback	1
kDevice	2
kBlackhole	3
Invalid	::std::numeric_limits<::fidl_union_tag_t>::max()

Defined at line 575 of file fidling/gen/sdk/fidl/fuchsia.net.interfaces/fuchsia.net.interfaces/hlcpp/fuchsia/net/interfaces/cpp/fidl.h

class Equality