class Topology

Defined at line 3258 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

A `Topology` specifies how processing elements are arranged within the hardware.

Public Members

static const fidl_type_t * FidlType

Public Methods

bool IsEmpty ()

Returns whether no field is set.

void Topology ()
void Topology (Topology && other)
const uint64_t & id ()

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

Defined at line 3268 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

bool has_id ()

Defined at line 3272 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

uint64_t * mutable_id ()

Unique ID for this topology. The scope of this id is only within the `SignalProcessing`

protocol lifespan, i.e. until the channel associated with the protocol is closed.

Required.

Defined at line 3280 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

void clear_id ()

Defined at line 3288 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

const ::std::vector< ::fuchsia::hardware::audio::signalprocessing::EdgePair> & processing_elements_edge_pairs ()

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT, RING_BUFFER, or PACKET_STREAM, and must end with an element

of type DAI_INTERCONNECT, RING_BUFFER, or PACKET_STREAM.

A DAI_INTERCONNECT element is _permitted_ to start or end an element sequence, but a

RING_BUFFER or PACKET_STREAM is _required_ to start or end one.

If a certain RING_BUFFER or PACKET_STREAM element is listed in an EdgePair as a

`processing_element_id_from`, then within that Topology this same element must NOT be

listed in another EdgePair as a `processing_element_id_to` (and vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

Defined at line 3324 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

bool has_processing_elements_edge_pairs ()

Defined at line 3328 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

::std::vector< ::fuchsia::hardware::audio::signalprocessing::EdgePair> * mutable_processing_elements_edge_pairs ()

Vector of processing elements edge pairs that specify connections between elements.

Processing elements are connected by edge pairs, to form multi-element pipelines.

A Topology can contain more than one distinct pipeline: the Topology need not be a single

interconnected sequence (e.g. Topology A->B->C D->E->F is valid).

To define multiple possible configurations where one possibility can be selected by the

client, return multiple `Topology` entries in `GetTopologies`.

If a device does support multiple Topology entries, then each specific Topology is not

required to include every Element. However, every element must be included in at least one

Topology.

Within each Topology, every sequence of connected elements must begin with an element

of type DAI_INTERCONNECT, RING_BUFFER, or PACKET_STREAM, and must end with an element

of type DAI_INTERCONNECT, RING_BUFFER, or PACKET_STREAM.

A DAI_INTERCONNECT element is _permitted_ to start or end an element sequence, but a

RING_BUFFER or PACKET_STREAM is _required_ to start or end one.

If a certain RING_BUFFER or PACKET_STREAM element is listed in an EdgePair as a

`processing_element_id_from`, then within that Topology this same element must NOT be

listed in another EdgePair as a `processing_element_id_to` (and vice versa).

As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may

contain `processing_element_id_from` and `processing_element_id_to` values that are equal.

However, this element must not _also_ connect to _other_ elements within the Topology (this

EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).

Required. Must contain at least one entry.

Defined at line 3360 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

void clear_processing_elements_edge_pairs ()

Defined at line 3368 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/hlcpp/fuchsia/hardware/audio/signalprocessing/cpp/fidl.h

Topology & set_id (uint64_t _value)
Topology & set_processing_elements_edge_pairs (::std::vector< ::fuchsia::hardware::audio::signalprocessing::EdgePair> _value)
void ~Topology ()
Topology & operator= (Topology && other)
::std::unique_ptr<Topology> New ()
void Encode (::fidl::Encoder * _encoder, size_t _offset, std::optional< ::fidl::HandleInformation> maybe_handle_info)
void Decode (::fidl::Decoder * _decoder, Topology * _value, size_t _offset)
zx_status_t Clone (Topology * _result)