template <>

class WireWeakAsyncBufferClientImpl

Defined at line 1541 of file fidling/gen/sdk/fidl/fuchsia.hardware.interconnect/fuchsia.hardware.interconnect/cpp/fidl/fuchsia.hardware.interconnect/cpp/wire_messaging.h

Public Methods

::fidl::internal::WireBufferThenable< ::fuchsia_hardware_interconnect::Path::SetBandwidth> SetBandwidth (::fuchsia_hardware_interconnect::wire::BandwidthRequest BandwidthRequest)

Sets the bandwidth interconnect path.

Caller provides the backing storage for FIDL message.