template <>class WireWeakAsyncBufferClientImpl
Defined at line 2480 of file fidling/gen/sdk/fidl/fuchsia.hardware.clockimpl/fuchsia.hardware.clockimpl/cpp/fidl/fuchsia.hardware.clockimpl/cpp/driver/wire_messaging.h
Public Methods
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::Enable> Enable (uint32_t id)Clock Gating Control.
Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::Disable> Disable (uint32_t id)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::IsEnabled> IsEnabled (uint32_t id)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::SetRate> SetRate (uint32_t id, uint64_t hz)Clock Frequency Scaling Control.
Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::QuerySupportedRate> QuerySupportedRate (uint32_t id, uint64_t hz)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::GetRate> GetRate (uint32_t id)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::SetInput> SetInput (uint32_t id, uint32_t idx)Clock input control.
Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::GetNumInputs> GetNumInputs (uint32_t id)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::GetInput> GetInput (uint32_t id)Caller provides the backing storage for FIDL message.
::fidl::internal::WireBufferThenable< ::fuchsia_hardware_clockimpl::ClockImpl::GetClockProperties> GetClockProperties ()Caller provides the backing storage for FIDL message.