template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 261 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h
Public Methods
::fuchsia_hardware_audio_signalprocessing::wire::PlugState Build ()Build and return the table. The builder should not be used after this.
bool has_plugged ()void clear_plugged ()Clears the plugged field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
bool & plugged ()Indicates whether the interconnect is currently plugged in.
Required
BuilderImpl & plugged (bool elem)Indicates whether the interconnect is currently plugged in.
Required
bool has_plug_state_time ()void clear_plug_state_time ()Clears the plug_state_time field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
int64_t & plug_state_time ()Indicates when the current `plugged` state was set, using `ZX_CLOCK_MONOTONIC`.
Cannot be negative.
Required.
BuilderImpl & plug_state_time (Wrapper_Ignore_Me_< ::fidl::ObjectView<int64_t>> elem)Indicates when the current `plugged` state was set, using `ZX_CLOCK_MONOTONIC`.
Cannot be negative.
Required.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::PlugState>> && frame)