template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 4045 of file fidling/gen/sdk/fidl/fuchsia.hardware.audio.signalprocessing/fuchsia.hardware.audio.signalprocessing/cpp/fidl/fuchsia.hardware.audio.signalprocessing/cpp/wire_types.h
Public Methods
::fuchsia_hardware_audio_signalprocessing::wire::Topology Build ()Build and return the table. The builder should not be used after this.
bool has_id ()void clear_id ()Clears the id field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint64_t & id ()Unique ID for this topology. The scope of this id is only within the `SignalProcessing`
protocol lifespan, i.e. until the channel associated with the protocol is closed.
Required.
BuilderImpl & id (Wrapper_Ignore_Me_< ::fidl::ObjectView<uint64_t>> elem)Unique ID for this topology. The scope of this id is only within the `SignalProcessing`
protocol lifespan, i.e. until the channel associated with the protocol is closed.
Required.
bool has_processing_elements_edge_pairs ()void clear_processing_elements_edge_pairs ()Clears the processing_elements_edge_pairs field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::EdgePair> & processing_elements_edge_pairs ()Vector of processing elements edge pairs that specify connections between elements.
Processing elements are connected by edge pairs, to form multi-element pipelines.
A Topology can contain more than one distinct pipeline: the Topology need not be a single
interconnected sequence (e.g. Topology A->B->C D->E->F is valid).
To define multiple possible configurations where one possibility can be selected by the
client, return multiple `Topology` entries in `GetTopologies`.
If a device does support multiple Topology entries, then each specific Topology is not
required to include every Element. However, every element must be included in at least one
Topology.
Within each Topology, every sequence of connected elements must begin with an element
of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type
DAI_INTERCONNECT or RING_BUFFER.
An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a
RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an
EdgeList entry as a `processing_element_id_from`, then within that Topology this same
element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and
vice versa).
As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may
contain `processing_element_id_from` and `processing_element_id_to` values that are equal.
However, this element must not _also_ connect to _other_ elements within the Topology (this
EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).
Required. Must contain at least one entry.
BuilderImpl & processing_elements_edge_pairs (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::EdgePair>>> elem)Vector of processing elements edge pairs that specify connections between elements.
Processing elements are connected by edge pairs, to form multi-element pipelines.
A Topology can contain more than one distinct pipeline: the Topology need not be a single
interconnected sequence (e.g. Topology A->B->C D->E->F is valid).
To define multiple possible configurations where one possibility can be selected by the
client, return multiple `Topology` entries in `GetTopologies`.
If a device does support multiple Topology entries, then each specific Topology is not
required to include every Element. However, every element must be included in at least one
Topology.
Within each Topology, every sequence of connected elements must begin with an element
of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type
DAI_INTERCONNECT or RING_BUFFER.
An DAI_INTERCONNECT element is _permitted_ to be the endpoint for an element sequence, but a
RING_BUFFER is _required_ to be one. If a certain RING_BUFFER element is listed in an
EdgeList entry as a `processing_element_id_from`, then within that Topology this same
element must NOT be listed in another EdgeList entry as a `processing_element_id_to` (and
vice versa).
As a special case, a DAI_INTERCONNECT element can refer to itself; i.e. an EdgePair may
contain `processing_element_id_from` and `processing_element_id_to` values that are equal.
However, this element must not _also_ connect to _other_ elements within the Topology (this
EdgePair must be the only one in `processing_elements_edge_pairs` to mention that element).
Required. Must contain at least one entry.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_audio_signalprocessing::wire::Topology, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_audio_signalprocessing::wire::Topology>> && frame)