template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 347 of file fidling/gen/sdk/fidl/fuchsia.hardware.amlogic.metadata/fuchsia.hardware.amlogic.metadata/cpp/fidl/fuchsia.hardware.amlogic.metadata/cpp/wire_types.h
Public Methods
::fuchsia_hardware_amlogic_metadata::wire::AmlI2cDelayValues Build ()Build and return the table. The builder should not be used after this.
bool has_quarter_clock_delay ()void clear_quarter_clock_delay ()Clears the quarter_clock_delay field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint16_t & quarter_clock_delay ()Getter for quarter_clock_delay.
BuilderImpl & quarter_clock_delay (uint16_t elem)Setter for quarter_clock_delay.
bool has_clock_low_delay ()void clear_clock_low_delay ()Clears the clock_low_delay field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint16_t & clock_low_delay ()Getter for clock_low_delay.
BuilderImpl & clock_low_delay (uint16_t elem)Setter for clock_low_delay.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_amlogic_metadata::wire::AmlI2cDelayValues, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_amlogic_metadata::wire::AmlI2cDelayValues>> && frame)