template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 314 of file fidling/gen/sdk/fidl/fuchsia.hardware.platform.bus/fuchsia.hardware.platform.bus/cpp/fidl/fuchsia.hardware.platform.bus/cpp/wire_types.h
Public Methods
::fuchsia_hardware_platform_bus::wire::Mmio Build ()Build and return the table. The builder should not be used after this.
bool has_base ()void clear_base ()Clears the base field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint64_t & base ()Physical address of MMIO region. Does not need to be page aligned.
BuilderImpl & base (Wrapper_Ignore_Me_< ::fidl::ObjectView<uint64_t>> elem)Physical address of MMIO region. Does not need to be page aligned.
bool has_length ()void clear_length ()Clears the length field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint64_t & length ()Length of MMIO region in bytes. Does not need to be page aligned.
BuilderImpl & length (Wrapper_Ignore_Me_< ::fidl::ObjectView<uint64_t>> elem)Length of MMIO region in bytes. Does not need to be page aligned.
bool has_name ()void clear_name ()Clears the name field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fidl::StringView & name ()Name that can be used to retrieve the Mmio using
[`fuchsia.hardware.platform.device/GetMmioByName`].
It is valid for this to be empty, however the resource will only be able
to be retrieved using [`fuchsia.hardware.platform.device/GetMmioById`].
BuilderImpl & name (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fidl::StringView>> elem)Name that can be used to retrieve the Mmio using
[`fuchsia.hardware.platform.device/GetMmioByName`].
It is valid for this to be empty, however the resource will only be able
to be retrieved using [`fuchsia.hardware.platform.device/GetMmioById`].
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_platform_bus::wire::Mmio, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_platform_bus::wire::Mmio>> && frame)