template <typename BuilderImpl>
class WireTableBaseBuilder
Defined at line 1181 of file fidling/gen/sdk/fidl/fuchsia.hardware.interconnect/fuchsia.hardware.interconnect/cpp/fidl/fuchsia.hardware.interconnect/cpp/wire_types.h
Public Methods
::fuchsia_hardware_interconnect::wire::Edge Build ()
Build and return the table. The builder should not be used after this.
bool has_src_node_id ()
void clear_src_node_id ()
Clears the src_node_id field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint32_t & src_node_id ()
Source where bus traffic may originate.
BuilderImpl & src_node_id (uint32_t elem)
Source where bus traffic may originate.
bool has_dst_node_id ()
void clear_dst_node_id ()
Clears the dst_node_id field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint32_t & dst_node_id ()
Destination where bus traffic may travel to.
BuilderImpl & dst_node_id (uint32_t elem)
Destination where bus traffic may travel to.
bool has_weight ()
void clear_weight ()
Clears the weight field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint32_t & weight ()
An optional weight to apply to the edge. Used for calculating the optimal
path from between two nodes. If there are multiple paths from one node to
another, the path will be calculated by optimizing for the smallest sum of
all edge weights along the path. If not provided, the weight is assumed to
be 1.
BuilderImpl & weight (uint32_t elem)
An optional weight to apply to the edge. Used for calculating the optimal
path from between two nodes. If there are multiple paths from one node to
another, the path will be calculated by optimizing for the smallest sum of
all edge weights along the path. If not provided, the weight is assumed to
be 1.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_interconnect::wire::Edge, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_interconnect::wire::Edge>> && frame)