template <typename BuilderImpl>class WireTableBaseBuilder
Defined at line 2060 of file fidling/gen/sdk/fidl/fuchsia.virtualaudio/fuchsia.virtualaudio/cpp/fidl/fuchsia.virtualaudio/cpp/wire_types.h
Public Methods
::fuchsia_virtualaudio::wire::Composite Build ()Build and return the table. The builder should not be used after this.
bool has_ring_buffers ()void clear_ring_buffers ()Clears the ring_buffers field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fidl::VectorView< ::fuchsia_virtualaudio::wire::CompositeRingBuffer> & ring_buffers ()Ring buffers configuration.
Required.
BuilderImpl & ring_buffers (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_virtualaudio::wire::CompositeRingBuffer>>> elem)Ring buffers configuration.
Required.
bool has_dai_interconnects ()void clear_dai_interconnects ()Clears the dai_interconnects field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fidl::VectorView< ::fuchsia_virtualaudio::wire::CompositeDaiInterconnect> & dai_interconnects ()DAI interconnects configurations.
Required.
BuilderImpl & dai_interconnects (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_virtualaudio::wire::CompositeDaiInterconnect>>> elem)DAI interconnects configurations.
Required.
bool has_clock_properties ()void clear_clock_properties ()Clears the clock_properties field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fuchsia_virtualaudio::wire::ClockProperties & clock_properties ()Configuration for the device's clock.
Required.
BuilderImpl & clock_properties (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fuchsia_virtualaudio::wire::ClockProperties>> elem)Configuration for the device's clock.
Required.
bool has_topologies ()void clear_topologies ()Clears the topologies field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::Topology> & topologies ()Topologies supported via the signalprocessing API.
Optional.
BuilderImpl & topologies (Wrapper_Ignore_Me_< ::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_audio_signalprocessing::wire::Topology>>> elem)Topologies supported via the signalprocessing API.
Optional.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_virtualaudio::wire::Composite, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_virtualaudio::wire::Composite>> && frame)