template <typename BuilderImpl>
class WireTableBaseBuilder
Defined at line 182 of file fidling/gen/sdk/fidl/fuchsia.hardware.pwm/fuchsia.hardware.pwm/cpp/fidl/fuchsia.hardware.pwm/cpp/wire_types.h
Public Methods
::fuchsia_hardware_pwm::wire::PwmChannelInfo Build ()
Build and return the table. The builder should not be used after this.
bool has_id ()
void clear_id ()
Clears the id field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint32_t & id ()
Unique id of PWM channel.
BuilderImpl & id (uint32_t elem)
Unique id of PWM channel.
bool has_skip_init ()
void clear_skip_init ()
Clears the skip_init field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
bool & skip_init ()
If true, the PWM channel will NOT be initialized. This is for use in situations where a
bootloader configuration must be preserved or the PWM channel may be under control of higher
exception level. (for a dvfs rail for example)
BuilderImpl & skip_init (bool elem)
If true, the PWM channel will NOT be initialized. This is for use in situations where a
bootloader configuration must be preserved or the PWM channel may be under control of higher
exception level. (for a dvfs rail for example)
bool has_polarity ()
void clear_polarity ()
Clears the polarity field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
bool & polarity ()
If true, the polarity will be inverted.
BuilderImpl & polarity (bool elem)
If true, the polarity will be inverted.
bool has_period_ns ()
void clear_period_ns ()
Clears the period_ns field.
This method should be used sparingly, such as only during tests, as it has
O(number_of_fields) complexity.
uint32_t & period_ns ()
PWM period in nanoseconds.
BuilderImpl & period_ns (uint32_t elem)
PWM period in nanoseconds.
Protected Methods
void WireTableBaseBuilder< ::fuchsia_hardware_pwm::wire::PwmChannelInfo, BuilderImpl> (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_pwm::wire::PwmChannelInfo>> && frame)